This is to use another AMD SEV-ES hardware assisted register swap,
more detail in 2/3. The patches are fairly independend but required in
this order.

The previous conversation is here:
https://lore.kernel.org/all/20221209043804.942352-1-aik@amd.com/

This is based on sha1
195df42eb64d Ingo Molnar "Merge branch into tip/master: 'x86/platform'"
in order to have recently added X86_FEATURE_NO_NESTED_DATA_BP cpu
feature.

Please comment. Thanks.



Alexey Kardashevskiy (3):
  x86/amd: Cache debug register values in percpu variables
  KVM: SEV: Enable data breakpoints in SEV-ES
  x86/sev: Do not handle #VC for DR7 read/write

 arch/x86/include/asm/debugreg.h        |  9 +++-
 arch/x86/include/asm/msr-index.h       |  1 +
 arch/x86/include/asm/svm.h             |  1 +
 arch/x86/kvm/svm/svm.h                 | 16 +++++--
 tools/arch/x86/include/asm/msr-index.h |  1 +
 arch/x86/kernel/cpu/amd.c              | 47 ++++++++++++++------
 arch/x86/kernel/hw_breakpoint.c        |  4 +-
 arch/x86/kernel/sev.c                  |  6 +++
 arch/x86/kvm/svm/sev.c                 | 29 ++++++++++++
 arch/x86/kvm/svm/svm.c                 |  3 +-
 10 files changed, 94 insertions(+), 23 deletions(-)

-- 
2.38.1