arch/arm64/boot/dts/qcom/sm8350.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
After switching interconnects to 2 cells, the SDHCI interconnects need
to get one more argument.
Fixes: 4f287e31ff5f ("arm64: dts: qcom: sm8350: Use 2 interconnect cells")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index e466dd839065..4efe79985186 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -2549,8 +2549,8 @@ sdhc_2: mmc@8804000 {
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "core", "xo";
resets = <&gcc GCC_SDCC2_BCR>;
- interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>,
- <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>;
+ interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
iommus = <&apps_smmu 0x4a0 0x0>;
power-domains = <&rpmhpd SM8350_CX>;
--
2.34.1
On Thu, 19 Jan 2023 11:54:34 +0100, Krzysztof Kozlowski wrote: > After switching interconnects to 2 cells, the SDHCI interconnects need > to get one more argument. > > Applied, thanks! [1/1] arm64: dts: qcom: sm8350: fixup SDHCI interconnect arguments commit: fc0ff3e702013c8af39f9967daaef1e565f7d165 Best regards, -- Bjorn Andersson <andersson@kernel.org>
On 19.01.2023 11:54, Krzysztof Kozlowski wrote: > After switching interconnects to 2 cells, the SDHCI interconnects need > to get one more argument. > > Fixes: 4f287e31ff5f ("arm64: dts: qcom: sm8350: Use 2 interconnect cells") > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- I think it may be worth including include/dt-bindings/interconnect/qcom,icc.h to get QCOM_ICC_TAG_ALWAYS (which is the default one set when the tag is 0) which is more telling.. But for the change, of course: Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm64/boot/dts/qcom/sm8350.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi > index e466dd839065..4efe79985186 100644 > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi > @@ -2549,8 +2549,8 @@ sdhc_2: mmc@8804000 { > <&rpmhcc RPMH_CXO_CLK>; > clock-names = "iface", "core", "xo"; > resets = <&gcc GCC_SDCC2_BCR>; > - interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>, > - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>; > + interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; > interconnect-names = "sdhc-ddr","cpu-sdhc"; > iommus = <&apps_smmu 0x4a0 0x0>; > power-domains = <&rpmhpd SM8350_CX>;
On 19/01/2023 11:59, Konrad Dybcio wrote: > > > On 19.01.2023 11:54, Krzysztof Kozlowski wrote: >> After switching interconnects to 2 cells, the SDHCI interconnects need >> to get one more argument. >> >> Fixes: 4f287e31ff5f ("arm64: dts: qcom: sm8350: Use 2 interconnect cells") >> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >> --- > I think it may be worth including > > include/dt-bindings/interconnect/qcom,icc.h > > to get QCOM_ICC_TAG_ALWAYS (which is the default > one set when the tag is 0) which is more telling.. This should be done in fixed commit 4f287e31ff5f, not here. I am just finishing that change. > > But for the change, of course: > > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Sure. Best regards, Krzysztof
© 2016 - 2025 Red Hat, Inc.