Let's support __HAVE_ARCH_PTE_SWP_EXCLUSIVE by stealing one bit
from the type. Generic MM currently only uses 5 bits for the type
(MAX_SWAPFILES_SHIFT), so the stolen bit is effectively unused.
The shift by 2 when converting between PTE and arch-specific swap entry
makes the swap PTE layout a little bit harder to decipher.
While at it, drop the comment from paulus---copy-and-paste leftover
from powerpc where we actually have _PAGE_HASHPTE---and mask the type in
__swp_entry_to_pte() as well.
Cc: Michal Simek <monstr@monstr.eu>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
arch/m68k/include/asm/mcf_pgtable.h | 4 +--
arch/microblaze/include/asm/pgtable.h | 45 +++++++++++++++++++++------
2 files changed, 37 insertions(+), 12 deletions(-)
diff --git a/arch/m68k/include/asm/mcf_pgtable.h b/arch/m68k/include/asm/mcf_pgtable.h
index 3f8f4d0e66dd..e573d7b649f7 100644
--- a/arch/m68k/include/asm/mcf_pgtable.h
+++ b/arch/m68k/include/asm/mcf_pgtable.h
@@ -46,8 +46,8 @@
#define _CACHEMASK040 (~0x060)
#define _PAGE_GLOBAL040 0x400 /* 68040 global bit, used for kva descs */
-/* We borrow bit 7 to store the exclusive marker in swap PTEs. */
-#define _PAGE_SWP_EXCLUSIVE 0x080
+/* We borrow bit 24 to store the exclusive marker in swap PTEs. */
+#define _PAGE_SWP_EXCLUSIVE CF_PAGE_NOCACHE
/*
* Externally used page protection values.
diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h
index 42f5988e998b..7e3de54bf426 100644
--- a/arch/microblaze/include/asm/pgtable.h
+++ b/arch/microblaze/include/asm/pgtable.h
@@ -131,10 +131,10 @@ extern pte_t *va_to_pte(unsigned long address);
* of the 16 available. Bit 24-26 of the TLB are cleared in the TLB
* miss handler. Bit 27 is PAGE_USER, thus selecting the correct
* zone.
- * - PRESENT *must* be in the bottom two bits because swap cache
- * entries use the top 30 bits. Because 4xx doesn't support SMP
- * anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30
- * is cleared in the TLB miss handler before the TLB entry is loaded.
+ * - PRESENT *must* be in the bottom two bits because swap PTEs use the top
+ * 30 bits. Because 4xx doesn't support SMP anyway, M is irrelevant so we
+ * borrow it for PAGE_PRESENT. Bit 30 is cleared in the TLB miss handler
+ * before the TLB entry is loaded.
* - All other bits of the PTE are loaded into TLBLO without
* * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
* software PTE bits. We actually use bits 21, 24, 25, and
@@ -155,6 +155,9 @@ extern pte_t *va_to_pte(unsigned long address);
#define _PAGE_ACCESSED 0x400 /* software: R: page referenced */
#define _PMD_PRESENT PAGE_MASK
+/* We borrow bit 24 to store the exclusive marker in swap PTEs. */
+#define _PAGE_SWP_EXCLUSIVE _PAGE_DIRTY
+
/*
* Some bits are unused...
*/
@@ -393,18 +396,40 @@ static inline unsigned long pmd_page_vaddr(pmd_t pmd)
extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
/*
- * Encode and decode a swap entry.
- * Note that the bits we use in a PTE for representing a swap entry
- * must not include the _PAGE_PRESENT bit, or the _PAGE_HASHPTE bit
- * (if used). -- paulus
+ * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
+ * are !pte_none() && !pte_present().
+ *
+ * 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
+ * 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
+ * <------------------ offset -------------------> E < type -> 0 0
+ *
+ * E is the exclusive marker that is not stored in swap entries.
*/
-#define __swp_type(entry) ((entry).val & 0x3f)
+#define __swp_type(entry) ((entry).val & 0x1f)
#define __swp_offset(entry) ((entry).val >> 6)
#define __swp_entry(type, offset) \
- ((swp_entry_t) { (type) | ((offset) << 6) })
+ ((swp_entry_t) { ((type) & 0x1f) | ((offset) << 6) })
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 2 })
#define __swp_entry_to_pte(x) ((pte_t) { (x).val << 2 })
+#define __HAVE_ARCH_PTE_SWP_EXCLUSIVE
+static inline int pte_swp_exclusive(pte_t pte)
+{
+ return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
+}
+
+static inline pte_t pte_swp_mkexclusive(pte_t pte)
+{
+ pte_val(pte) |= _PAGE_SWP_EXCLUSIVE;
+ return pte;
+}
+
+static inline pte_t pte_swp_clear_exclusive(pte_t pte)
+{
+ pte_val(pte) &= ~_PAGE_SWP_EXCLUSIVE;
+ return pte;
+}
+
extern unsigned long iopa(unsigned long addr);
/* Values for nocacheflag and cmode */
--
2.39.0Hi David,
On Fri, Jan 13, 2023 at 6:16 PM David Hildenbrand <david@redhat.com> wrote:
> Let's support __HAVE_ARCH_PTE_SWP_EXCLUSIVE by stealing one bit
> from the type. Generic MM currently only uses 5 bits for the type
> (MAX_SWAPFILES_SHIFT), so the stolen bit is effectively unused.
>
> The shift by 2 when converting between PTE and arch-specific swap entry
> makes the swap PTE layout a little bit harder to decipher.
>
> While at it, drop the comment from paulus---copy-and-paste leftover
> from powerpc where we actually have _PAGE_HASHPTE---and mask the type in
> __swp_entry_to_pte() as well.
>
> Cc: Michal Simek <monstr@monstr.eu>
> Signed-off-by: David Hildenbrand <david@redhat.com>
Thanks for your patch, which is now commit b5c88f21531c3457
("microblaze/mm: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE") in
> arch/m68k/include/asm/mcf_pgtable.h | 4 +--
What is this m68k change doing here?
Sorry for not noticing this earlier.
Furthermore, several things below look strange to me...
> arch/microblaze/include/asm/pgtable.h | 45 +++++++++++++++++++++------
> 2 files changed, 37 insertions(+), 12 deletions(-)
>
> diff --git a/arch/m68k/include/asm/mcf_pgtable.h b/arch/m68k/include/asm/mcf_pgtable.h
> index 3f8f4d0e66dd..e573d7b649f7 100644
> --- a/arch/m68k/include/asm/mcf_pgtable.h
> +++ b/arch/m68k/include/asm/mcf_pgtable.h
> @@ -46,8 +46,8 @@
> #define _CACHEMASK040 (~0x060)
> #define _PAGE_GLOBAL040 0x400 /* 68040 global bit, used for kva descs */
>
> -/* We borrow bit 7 to store the exclusive marker in swap PTEs. */
> -#define _PAGE_SWP_EXCLUSIVE 0x080
> +/* We borrow bit 24 to store the exclusive marker in swap PTEs. */
> +#define _PAGE_SWP_EXCLUSIVE CF_PAGE_NOCACHE
CF_PAGE_NOCACHE is 0x80, so this is still bit 7, thus the new comment
is wrong?
>
> /*
> * Externally used page protection values.
> diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h
> index 42f5988e998b..7e3de54bf426 100644
> --- a/arch/microblaze/include/asm/pgtable.h
> +++ b/arch/microblaze/include/asm/pgtable.h
> @@ -131,10 +131,10 @@ extern pte_t *va_to_pte(unsigned long address);
> * of the 16 available. Bit 24-26 of the TLB are cleared in the TLB
> * miss handler. Bit 27 is PAGE_USER, thus selecting the correct
> * zone.
> - * - PRESENT *must* be in the bottom two bits because swap cache
> - * entries use the top 30 bits. Because 4xx doesn't support SMP
> - * anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30
> - * is cleared in the TLB miss handler before the TLB entry is loaded.
> + * - PRESENT *must* be in the bottom two bits because swap PTEs use the top
> + * 30 bits. Because 4xx doesn't support SMP anyway, M is irrelevant so we
> + * borrow it for PAGE_PRESENT. Bit 30 is cleared in the TLB miss handler
> + * before the TLB entry is loaded.
So the PowerPC 4xx comment is still here?
> * - All other bits of the PTE are loaded into TLBLO without
> * * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
> * software PTE bits. We actually use bits 21, 24, 25, and
> @@ -155,6 +155,9 @@ extern pte_t *va_to_pte(unsigned long address);
> #define _PAGE_ACCESSED 0x400 /* software: R: page referenced */
> #define _PMD_PRESENT PAGE_MASK
>
> +/* We borrow bit 24 to store the exclusive marker in swap PTEs. */
> +#define _PAGE_SWP_EXCLUSIVE _PAGE_DIRTY
_PAGE_DIRTY is 0x80, so this is also bit 7, thus the new comment is
wrong?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On 26.02.23 21:13, Geert Uytterhoeven wrote:
> Hi David,
Hi Geert,
>
> On Fri, Jan 13, 2023 at 6:16 PM David Hildenbrand <david@redhat.com> wrote:
>> Let's support __HAVE_ARCH_PTE_SWP_EXCLUSIVE by stealing one bit
>> from the type. Generic MM currently only uses 5 bits for the type
>> (MAX_SWAPFILES_SHIFT), so the stolen bit is effectively unused.
>>
>> The shift by 2 when converting between PTE and arch-specific swap entry
>> makes the swap PTE layout a little bit harder to decipher.
>>
>> While at it, drop the comment from paulus---copy-and-paste leftover
>> from powerpc where we actually have _PAGE_HASHPTE---and mask the type in
>> __swp_entry_to_pte() as well.
>>
>> Cc: Michal Simek <monstr@monstr.eu>
>> Signed-off-by: David Hildenbrand <david@redhat.com>
>
> Thanks for your patch, which is now commit b5c88f21531c3457
> ("microblaze/mm: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE") in
>
Right, it went upstream, so we can only fixup.
>> arch/m68k/include/asm/mcf_pgtable.h | 4 +--
>
> What is this m68k change doing here?
> Sorry for not noticing this earlier.
Thanks for the late review, still valuable :)
That hunk should have gone into the previous patch, looks like I messed
that up when reworking.
>
> Furthermore, several things below look strange to me...
>
>> arch/microblaze/include/asm/pgtable.h | 45 +++++++++++++++++++++------
>> 2 files changed, 37 insertions(+), 12 deletions(-)
>>
>> diff --git a/arch/m68k/include/asm/mcf_pgtable.h b/arch/m68k/include/asm/mcf_pgtable.h
>> index 3f8f4d0e66dd..e573d7b649f7 100644
>> --- a/arch/m68k/include/asm/mcf_pgtable.h
>> +++ b/arch/m68k/include/asm/mcf_pgtable.h
>> @@ -46,8 +46,8 @@
>> #define _CACHEMASK040 (~0x060)
>> #define _PAGE_GLOBAL040 0x400 /* 68040 global bit, used for kva descs */
>>
>> -/* We borrow bit 7 to store the exclusive marker in swap PTEs. */
>> -#define _PAGE_SWP_EXCLUSIVE 0x080
>> +/* We borrow bit 24 to store the exclusive marker in swap PTEs. */
>> +#define _PAGE_SWP_EXCLUSIVE CF_PAGE_NOCACHE
>
> CF_PAGE_NOCACHE is 0x80, so this is still bit 7, thus the new comment
> is wrong?
You're right, it's still bit 7 (and we use LSB-0 bit numbering in that
file). I'll send a fixup.
>
>>
>> /*
>> * Externally used page protection values.
>> diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h
>> index 42f5988e998b..7e3de54bf426 100644
>> --- a/arch/microblaze/include/asm/pgtable.h
>> +++ b/arch/microblaze/include/asm/pgtable.h
>> @@ -131,10 +131,10 @@ extern pte_t *va_to_pte(unsigned long address);
>> * of the 16 available. Bit 24-26 of the TLB are cleared in the TLB
>> * miss handler. Bit 27 is PAGE_USER, thus selecting the correct
>> * zone.
>> - * - PRESENT *must* be in the bottom two bits because swap cache
>> - * entries use the top 30 bits. Because 4xx doesn't support SMP
>> - * anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30
>> - * is cleared in the TLB miss handler before the TLB entry is loaded.
>> + * - PRESENT *must* be in the bottom two bits because swap PTEs use the top
>> + * 30 bits. Because 4xx doesn't support SMP anyway, M is irrelevant so we
>> + * borrow it for PAGE_PRESENT. Bit 30 is cleared in the TLB miss handler
>> + * before the TLB entry is loaded.
>
> So the PowerPC 4xx comment is still here?
I only dropped the comment above __swp_type(). I guess you mean that we
could also drop the "Because 4xx doesn't support SMP anyway, M is
irrelevant so we borrow it for PAGE_PRESENT." sentence, correct? Not
sure about the "Bit 30 is cleared in the TLB miss handler" comment, if
that can similarly be dropped.
>
>> * - All other bits of the PTE are loaded into TLBLO without
>> * * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
>> * software PTE bits. We actually use bits 21, 24, 25, and
>> @@ -155,6 +155,9 @@ extern pte_t *va_to_pte(unsigned long address);
>> #define _PAGE_ACCESSED 0x400 /* software: R: page referenced */
>> #define _PMD_PRESENT PAGE_MASK
>>
>> +/* We borrow bit 24 to store the exclusive marker in swap PTEs. */
>> +#define _PAGE_SWP_EXCLUSIVE _PAGE_DIRTY
>
> _PAGE_DIRTY is 0x80, so this is also bit 7, thus the new comment is
> wrong?
In the example, I use MSB-0 bit numbering (which I determined to be
correct in microblaze context eventually, but I got confused a couple a
times because it's very inconsistent). That should be MSB-0 bit 24.
Thanks!
--
Thanks,
David / dhildenb
Hi David,
On Mon, Feb 27, 2023 at 2:31 PM David Hildenbrand <david@redhat.com> wrote:
> On 26.02.23 21:13, Geert Uytterhoeven wrote:
> > On Fri, Jan 13, 2023 at 6:16 PM David Hildenbrand <david@redhat.com> wrote:
> >> Let's support __HAVE_ARCH_PTE_SWP_EXCLUSIVE by stealing one bit
> >> from the type. Generic MM currently only uses 5 bits for the type
> >> (MAX_SWAPFILES_SHIFT), so the stolen bit is effectively unused.
> >>
> >> The shift by 2 when converting between PTE and arch-specific swap entry
> >> makes the swap PTE layout a little bit harder to decipher.
> >>
> >> While at it, drop the comment from paulus---copy-and-paste leftover
> >> from powerpc where we actually have _PAGE_HASHPTE---and mask the type in
> >> __swp_entry_to_pte() as well.
> >>
> >> Cc: Michal Simek <monstr@monstr.eu>
> >> Signed-off-by: David Hildenbrand <david@redhat.com>
> >
> > Thanks for your patch, which is now commit b5c88f21531c3457
> > ("microblaze/mm: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE") in
> >
>
> Right, it went upstream, so we can only fixup.
>
> >> arch/m68k/include/asm/mcf_pgtable.h | 4 +--
> >
> > What is this m68k change doing here?
> > Sorry for not noticing this earlier.
>
> Thanks for the late review, still valuable :)
>
> That hunk should have gone into the previous patch, looks like I messed
> that up when reworking.
>
> >
> > Furthermore, several things below look strange to me...
> >
> >> arch/microblaze/include/asm/pgtable.h | 45 +++++++++++++++++++++------
> >> 2 files changed, 37 insertions(+), 12 deletions(-)
> >>
> >> diff --git a/arch/m68k/include/asm/mcf_pgtable.h b/arch/m68k/include/asm/mcf_pgtable.h
> >> index 3f8f4d0e66dd..e573d7b649f7 100644
> >> --- a/arch/m68k/include/asm/mcf_pgtable.h
> >> +++ b/arch/m68k/include/asm/mcf_pgtable.h
> >> @@ -46,8 +46,8 @@
> >> #define _CACHEMASK040 (~0x060)
> >> #define _PAGE_GLOBAL040 0x400 /* 68040 global bit, used for kva descs */
> >>
> >> -/* We borrow bit 7 to store the exclusive marker in swap PTEs. */
> >> -#define _PAGE_SWP_EXCLUSIVE 0x080
> >> +/* We borrow bit 24 to store the exclusive marker in swap PTEs. */
> >> +#define _PAGE_SWP_EXCLUSIVE CF_PAGE_NOCACHE
> >
> > CF_PAGE_NOCACHE is 0x80, so this is still bit 7, thus the new comment
> > is wrong?
>
> You're right, it's still bit 7 (and we use LSB-0 bit numbering in that
> file). I'll send a fixup.
OK.
> >> /*
> >> * Externally used page protection values.
> >> diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h
> >> index 42f5988e998b..7e3de54bf426 100644
> >> --- a/arch/microblaze/include/asm/pgtable.h
> >> +++ b/arch/microblaze/include/asm/pgtable.h
> >> @@ -131,10 +131,10 @@ extern pte_t *va_to_pte(unsigned long address);
> >> * of the 16 available. Bit 24-26 of the TLB are cleared in the TLB
> >> * miss handler. Bit 27 is PAGE_USER, thus selecting the correct
> >> * zone.
> >> - * - PRESENT *must* be in the bottom two bits because swap cache
> >> - * entries use the top 30 bits. Because 4xx doesn't support SMP
> >> - * anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30
> >> - * is cleared in the TLB miss handler before the TLB entry is loaded.
> >> + * - PRESENT *must* be in the bottom two bits because swap PTEs use the top
> >> + * 30 bits. Because 4xx doesn't support SMP anyway, M is irrelevant so we
> >> + * borrow it for PAGE_PRESENT. Bit 30 is cleared in the TLB miss handler
> >> + * before the TLB entry is loaded.
> >
> > So the PowerPC 4xx comment is still here?
>
> I only dropped the comment above __swp_type(). I guess you mean that we
> could also drop the "Because 4xx doesn't support SMP anyway, M is
> irrelevant so we borrow it for PAGE_PRESENT." sentence, correct? Not
Yes, that's what I meant.
> sure about the "Bit 30 is cleared in the TLB miss handler" comment, if
> that can similarly be dropped.
No idea, didn't check. But if it was copied from PPC, chances are
high it's no longer true....
> >> * - All other bits of the PTE are loaded into TLBLO without
> >> * * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
> >> * software PTE bits. We actually use bits 21, 24, 25, and
> >> @@ -155,6 +155,9 @@ extern pte_t *va_to_pte(unsigned long address);
> >> #define _PAGE_ACCESSED 0x400 /* software: R: page referenced */
> >> #define _PMD_PRESENT PAGE_MASK
> >>
> >> +/* We borrow bit 24 to store the exclusive marker in swap PTEs. */
> >> +#define _PAGE_SWP_EXCLUSIVE _PAGE_DIRTY
> >
> > _PAGE_DIRTY is 0x80, so this is also bit 7, thus the new comment is
> > wrong?
>
> In the example, I use MSB-0 bit numbering (which I determined to be
> correct in microblaze context eventually, but I got confused a couple a
> times because it's very inconsistent). That should be MSB-0 bit 24.
Thanks, TIL microblaze uses IBM bit numbering...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
>>>> /* >>>> * Externally used page protection values. >>>> diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h >>>> index 42f5988e998b..7e3de54bf426 100644 >>>> --- a/arch/microblaze/include/asm/pgtable.h >>>> +++ b/arch/microblaze/include/asm/pgtable.h >>>> @@ -131,10 +131,10 @@ extern pte_t *va_to_pte(unsigned long address); >>>> * of the 16 available. Bit 24-26 of the TLB are cleared in the TLB >>>> * miss handler. Bit 27 is PAGE_USER, thus selecting the correct >>>> * zone. >>>> - * - PRESENT *must* be in the bottom two bits because swap cache >>>> - * entries use the top 30 bits. Because 4xx doesn't support SMP >>>> - * anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30 >>>> - * is cleared in the TLB miss handler before the TLB entry is loaded. >>>> + * - PRESENT *must* be in the bottom two bits because swap PTEs use the top >>>> + * 30 bits. Because 4xx doesn't support SMP anyway, M is irrelevant so we >>>> + * borrow it for PAGE_PRESENT. Bit 30 is cleared in the TLB miss handler >>>> + * before the TLB entry is loaded. >>> >>> So the PowerPC 4xx comment is still here? >> >> I only dropped the comment above __swp_type(). I guess you mean that we >> could also drop the "Because 4xx doesn't support SMP anyway, M is >> irrelevant so we borrow it for PAGE_PRESENT." sentence, correct? Not > > Yes, that's what I meant. > >> sure about the "Bit 30 is cleared in the TLB miss handler" comment, if >> that can similarly be dropped. > > No idea, didn't check. But if it was copied from PPC, chances are > high it's no longer true.... I'll have a look. > >>>> * - All other bits of the PTE are loaded into TLBLO without >>>> * * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for >>>> * software PTE bits. We actually use bits 21, 24, 25, and >>>> @@ -155,6 +155,9 @@ extern pte_t *va_to_pte(unsigned long address); >>>> #define _PAGE_ACCESSED 0x400 /* software: R: page referenced */ >>>> #define _PMD_PRESENT PAGE_MASK >>>> >>>> +/* We borrow bit 24 to store the exclusive marker in swap PTEs. */ >>>> +#define _PAGE_SWP_EXCLUSIVE _PAGE_DIRTY >>> >>> _PAGE_DIRTY is 0x80, so this is also bit 7, thus the new comment is >>> wrong? >> >> In the example, I use MSB-0 bit numbering (which I determined to be >> correct in microblaze context eventually, but I got confused a couple a >> times because it's very inconsistent). That should be MSB-0 bit 24. > > Thanks, TIL microblaze uses IBM bit numbering... I assume IBM bit numbering corresponds to MSB-0 bit numbering, correct? I recall that I used the comment above "/* Definitions for MicroBlaze. */" as an orientation. 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RPN..................... 0 0 EX WR ZSEL....... W I M G So ... either we adjust both or we leave it as is. (again, depends on what the right thing to to is -- which I don't know :) ) -- Thanks, David / dhildenb
Hi David,
On Mon, Feb 27, 2023 at 6:01 PM David Hildenbrand <david@redhat.com> wrote:
> >>>> /*
> >>>> * Externally used page protection values.
> >>>> diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h
> >>>> index 42f5988e998b..7e3de54bf426 100644
> >>>> --- a/arch/microblaze/include/asm/pgtable.h
> >>>> +++ b/arch/microblaze/include/asm/pgtable.h
> >>>> * - All other bits of the PTE are loaded into TLBLO without
> >>>> * * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
> >>>> * software PTE bits. We actually use bits 21, 24, 25, and
> >>>> @@ -155,6 +155,9 @@ extern pte_t *va_to_pte(unsigned long address);
> >>>> #define _PAGE_ACCESSED 0x400 /* software: R: page referenced */
> >>>> #define _PMD_PRESENT PAGE_MASK
> >>>>
> >>>> +/* We borrow bit 24 to store the exclusive marker in swap PTEs. */
> >>>> +#define _PAGE_SWP_EXCLUSIVE _PAGE_DIRTY
> >>>
> >>> _PAGE_DIRTY is 0x80, so this is also bit 7, thus the new comment is
> >>> wrong?
> >>
> >> In the example, I use MSB-0 bit numbering (which I determined to be
> >> correct in microblaze context eventually, but I got confused a couple a
> >> times because it's very inconsistent). That should be MSB-0 bit 24.
> >
> > Thanks, TIL microblaze uses IBM bit numbering...
>
> I assume IBM bit numbering corresponds to MSB-0 bit numbering, correct?
Correct, as seen in s370 and PowerPC manuals...
> I recall that I used the comment above "/* Definitions for MicroBlaze.
> */" as an orientation.
>
> 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
> RPN..................... 0 0 EX WR ZSEL....... W I M G
Indeed, that's where I noticed the "unconventional" numbering...
> So ... either we adjust both or we leave it as is. (again, depends on
> what the right thing to to is -- which I don't know :) )
It depends whether you want to match the hardware documentation,
or the Linux BIT() macro and friends...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On 27.02.23 20:46, Geert Uytterhoeven wrote: > Hi David, > > On Mon, Feb 27, 2023 at 6:01 PM David Hildenbrand <david@redhat.com> wrote: >>>>>> /* >>>>>> * Externally used page protection values. >>>>>> diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h >>>>>> index 42f5988e998b..7e3de54bf426 100644 >>>>>> --- a/arch/microblaze/include/asm/pgtable.h >>>>>> +++ b/arch/microblaze/include/asm/pgtable.h > >>>>>> * - All other bits of the PTE are loaded into TLBLO without >>>>>> * * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for >>>>>> * software PTE bits. We actually use bits 21, 24, 25, and >>>>>> @@ -155,6 +155,9 @@ extern pte_t *va_to_pte(unsigned long address); >>>>>> #define _PAGE_ACCESSED 0x400 /* software: R: page referenced */ >>>>>> #define _PMD_PRESENT PAGE_MASK >>>>>> >>>>>> +/* We borrow bit 24 to store the exclusive marker in swap PTEs. */ >>>>>> +#define _PAGE_SWP_EXCLUSIVE _PAGE_DIRTY >>>>> >>>>> _PAGE_DIRTY is 0x80, so this is also bit 7, thus the new comment is >>>>> wrong? >>>> >>>> In the example, I use MSB-0 bit numbering (which I determined to be >>>> correct in microblaze context eventually, but I got confused a couple a >>>> times because it's very inconsistent). That should be MSB-0 bit 24. >>> >>> Thanks, TIL microblaze uses IBM bit numbering... >> >> I assume IBM bit numbering corresponds to MSB-0 bit numbering, correct? > > Correct, as seen in s370 and PowerPC manuals... Good, I have some solid s390x background, but thinking about the term "IBM PC" made me double-check that we're talking about the same thing ;) > >> I recall that I used the comment above "/* Definitions for MicroBlaze. >> */" as an orientation. >> >> 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31 >> RPN..................... 0 0 EX WR ZSEL....... W I M G > > Indeed, that's where I noticed the "unconventional" numbering... > >> So ... either we adjust both or we leave it as is. (again, depends on >> what the right thing to to is -- which I don't know :) ) > > It depends whether you want to match the hardware documentation, > or the Linux BIT() macro and friends... The hardware documentation, so we should be good. Thanks! -- Thanks, David / dhildenb
© 2016 - 2026 Red Hat, Inc.