Add support for the QMC (QUICC Multichannel Controller)
available in some PowerQUICC SoC such as MPC885 or MPC866.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
.../bindings/soc/fsl/cpm_qe/fsl,qmc.yaml | 167 ++++++++++++++++++
1 file changed, 167 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
new file mode 100644
index 000000000000..caf71f3a3f3f
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
@@ -0,0 +1,167 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: PowerQUICC CPM QUICC Multichannel Controller (QMC)
+
+maintainers:
+ - Herve Codina <herve.codina@bootlin.com>
+
+description: |
+ The QMC (QUICC Multichannel Controller) emulates up to 64 channels within
+ one serial controller using the same TDM physical interface routed from
+ TSA.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - fsl,mpc885-scc-qmc
+ - fsl,mpc866-scc-qmc
+ - const: fsl,cpm1-scc-qmc
+
+ reg:
+ items:
+ - description: SCC (Serial communication controller) register base
+ - description: SCC parameter ram base
+ - description: Dual port ram base
+
+ reg-names:
+ items:
+ - const: scc_regs
+ - const: scc_pram
+ - const: dpram
+
+ interrupts:
+ description: SCC interrupt line in the CPM interrupt controller
+
+ fsl,cpm-command:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Cf. soc/fsl/cpm_qe/cpm.txt
+
+ tsa:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to the TSA
+
+ tsa-cell-id:
+ enum: [1, 2, 3]
+ description: |
+ TSA cell ID (dt-bindings/soc/fsl-tsa.h defines these values)
+ - 1: SCC2
+ - 2: SCC3
+ - 3: SCC4
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ '#chan-cells':
+ const: 1
+
+patternProperties:
+ "^channel@([0-9]|[1-5][0-9]|6[0-3])$":
+ description:
+ A channel managed by this controller
+ type: object
+
+ properties:
+ reg:
+ minimum: 0
+ maximum: 63
+ description:
+ The channel number
+
+ fsl,mode:
+ $ref: /schemas/types.yaml#/definitions/string
+ enum: [transparent, hdlc]
+ default: transparent
+ description: Operational mode
+
+ fsl,reverse-data:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ The bit order as seen on the channels is reversed,
+ transmitting/receiving the MSB of each octet first.
+ This flag is used only in 'transparent' mode.
+
+ tx-ts-mask:
+ $ref: /schemas/types.yaml#/definitions/uint64
+ description:
+ Channel assigned Tx time-slots within the Tx time-slots routed
+ by the TSA to this cell.
+
+ rx-ts-mask:
+ $ref: /schemas/types.yaml#/definitions/uint64
+ description:
+ Channel assigned Rx time-slots within the Rx time-slots routed
+ by the TSA to this cell.
+
+ required:
+ - reg
+ - tx-ts-mask
+ - rx-ts-mask
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - tsa
+ - tsa-cell-id
+ - '#address-cells'
+ - '#size-cells'
+ - '#chan-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/soc/fsl-tsa.h>
+
+ scc_qmc@a60 {
+ compatible = "fsl,mpc885-scc-qmc", "fsl,cpm1-scc-qmc";
+ reg = <0xa60 0x20>,
+ <0x3f00 0xc0>,
+ <0x2000 0x1000>;
+ reg-names = "scc_regs", "scc_pram", "dpram";
+ interrupts = <27>;
+ interrupt-parent = <&CPM_PIC>;
+ fsl,cpm-command = <0xc0>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #chan-cells = <1>;
+
+ tsa = <&tsa>;
+ tsa-cell-id = <FSL_CPM_TSA_SCC4>;
+
+ channel@16 {
+ /* Ch16 : First 4 even TS from all routed from TSA */
+ reg = <16>;
+ fsl,mode = "transparent";
+ fsl,reverse-data;
+ tx-ts-mask = <0x00000000 0x000000AA>;
+ rx-ts-mask = <0x00000000 0x000000AA>;
+ };
+
+ channel@17 {
+ /* Ch17 : First 4 odd TS from all routed from TSA */
+ reg = <17>;
+ fsl,mode = "transparent";
+ fsl,reverse-data;
+ tx-ts-mask = <0x00000000 0x00000055>;
+ rx-ts-mask = <0x00000000 0x00000055>;
+ };
+
+ channel@19 {
+ /* Ch19 : 8 TS (TS 8..15) from all routed from TSA */
+ reg = <19>;
+ fsl,mode = "hdlc";
+ tx-ts-mask = <0x00000000 0x0000FF00>;
+ rx-ts-mask = <0x00000000 0x0000FF00>;
+ };
+ };
--
2.38.1On 06/01/2023 17:37, Herve Codina wrote:
> Add support for the QMC (QUICC Multichannel Controller)
> available in some PowerQUICC SoC such as MPC885 or MPC866.
>
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> ---
> .../bindings/soc/fsl/cpm_qe/fsl,qmc.yaml | 167 ++++++++++++++++++
> 1 file changed, 167 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
>
> diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
> new file mode 100644
> index 000000000000..caf71f3a3f3f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
> @@ -0,0 +1,167 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qmc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: PowerQUICC CPM QUICC Multichannel Controller (QMC)
> +
> +maintainers:
> + - Herve Codina <herve.codina@bootlin.com>
> +
> +description: |
> + The QMC (QUICC Multichannel Controller) emulates up to 64 channels within
> + one serial controller using the same TDM physical interface routed from
> + TSA.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - fsl,mpc885-scc-qmc
> + - fsl,mpc866-scc-qmc
> + - const: fsl,cpm1-scc-qmc
> +
> + reg:
> + items:
> + - description: SCC (Serial communication controller) register base
> + - description: SCC parameter ram base
> + - description: Dual port ram base
> +
> + reg-names:
> + items:
> + - const: scc_regs
> + - const: scc_pram
> + - const: dpram
> +
> + interrupts:
> + description: SCC interrupt line in the CPM interrupt controller
Missing constraints.
> +
> + fsl,cpm-command:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: Cf. soc/fsl/cpm_qe/cpm.txt
Missing description.
> +
> + tsa:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: phandle to the TSA
Missing vendor prefix. Does not look like a generic property.
> +
> + tsa-cell-id:
> + enum: [1, 2, 3]
> + description: |
> + TSA cell ID (dt-bindings/soc/fsl-tsa.h defines these values)
> + - 1: SCC2
> + - 2: SCC3
> + - 3: SCC4
> +
> + '#address-cells':
> + const: 1
> +
> + '#size-cells':
> + const: 0
> +
> + '#chan-cells':
> + const: 1
> +
> +patternProperties:
> + "^channel@([0-9]|[1-5][0-9]|6[0-3])$":
> + description:
> + A channel managed by this controller
> + type: object
> +
> + properties:
> + reg:
> + minimum: 0
> + maximum: 63
> + description:
> + The channel number
> +
> + fsl,mode:
> + $ref: /schemas/types.yaml#/definitions/string
> + enum: [transparent, hdlc]
> + default: transparent
> + description: Operational mode
And what do they mean?
> +
> + fsl,reverse-data:
> + $ref: /schemas/types.yaml#/definitions/flag
> + description:
> + The bit order as seen on the channels is reversed,
> + transmitting/receiving the MSB of each octet first.
> + This flag is used only in 'transparent' mode.
> +
> + tx-ts-mask:
Missing vendor prefix.
> + $ref: /schemas/types.yaml#/definitions/uint64
> + description:
> + Channel assigned Tx time-slots within the Tx time-slots routed
> + by the TSA to this cell.
> +
> + rx-ts-mask:
> + $ref: /schemas/types.yaml#/definitions/uint64
> + description:
> + Channel assigned Rx time-slots within the Rx time-slots routed
> + by the TSA to this cell.
> +
> + required:
> + - reg
> + - tx-ts-mask
> + - rx-ts-mask
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - interrupts
> + - tsa
> + - tsa-cell-id
> + - '#address-cells'
> + - '#size-cells'
> + - '#chan-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/soc/fsl-tsa.h>
> +
> + scc_qmc@a60 {
No underscores in node names.
Node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
> + compatible = "fsl,mpc885-scc-qmc", "fsl,cpm1-scc-qmc";
> + reg = <0xa60 0x20>,
> + <0x3f00 0xc0>,
> + <0x2000 0x1000>;
> + reg-names = "scc_regs", "scc_pram", "dpram";
> + interrupts = <27>;
> + interrupt-parent = <&CPM_PIC>;
> + fsl,cpm-command = <0xc0>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #chan-cells = <1>;
> +
> + tsa = <&tsa>;
> + tsa-cell-id = <FSL_CPM_TSA_SCC4>;
> +
> + channel@16 {
> + /* Ch16 : First 4 even TS from all routed from TSA */
> + reg = <16>;
> + fsl,mode = "transparent";
> + fsl,reverse-data;
> + tx-ts-mask = <0x00000000 0x000000AA>;
> + rx-ts-mask = <0x00000000 0x000000AA>;
Keep case consistent. lower-case hex.
Best regards,
Krzysztof
Hi Krzysztof,
On Sun, 8 Jan 2023 16:14:47 +0100
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
[...]
> > +
> > + interrupts:
> > + description: SCC interrupt line in the CPM interrupt controller
>
> Missing constraints.
'maxItems: 1' will be added in v3
>
> > +
> > + fsl,cpm-command:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + description: Cf. soc/fsl/cpm_qe/cpm.txt
>
> Missing description.
'fsl,cpm-command' will be removed in v3.
The value needed is determined based on other information.
This is not needed in the DT.
>
> > +
> > + tsa:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description: phandle to the TSA
>
> Missing vendor prefix. Does not look like a generic property.
Will be be changed to 'fsl,tsa'
and also 'tsa-cell-id' will be changed to 'fsl,tsa-cell-id'
>
[...]
> > +
> > +patternProperties:
> > + "^channel@([0-9]|[1-5][0-9]|6[0-3])$":
> > + description:
> > + A channel managed by this controller
> > + type: object
> > +
> > + properties:
> > + reg:
> > + minimum: 0
> > + maximum: 63
> > + description:
> > + The channel number
> > +
> > + fsl,mode:
> > + $ref: /schemas/types.yaml#/definitions/string
> > + enum: [transparent, hdlc]
> > + default: transparent
> > + description: Operational mode
>
> And what do they mean?
I will change with
description: |
The channel operational mode
- hdlc: The channel handles HDLC frames
- transparent: The channel handles raw data without any processing
>
> > +
> > + fsl,reverse-data:
> > + $ref: /schemas/types.yaml#/definitions/flag
> > + description:
> > + The bit order as seen on the channels is reversed,
> > + transmitting/receiving the MSB of each octet first.
> > + This flag is used only in 'transparent' mode.
> > +
> > + tx-ts-mask:
>
> Missing vendor prefix.
Will be added, also on rx-ts-mask.
>
> > + $ref: /schemas/types.yaml#/definitions/uint64
> > + description:
> > + Channel assigned Tx time-slots within the Tx time-slots routed
> > + by the TSA to this cell.
> > +
> > + rx-ts-mask:
> > + $ref: /schemas/types.yaml#/definitions/uint64
> > + description:
> > + Channel assigned Rx time-slots within the Rx time-slots routed
> > + by the TSA to this cell.
> > +
> > + required:
> > + - reg
> > + - tx-ts-mask
> > + - rx-ts-mask
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - reg-names
> > + - interrupts
> > + - tsa
> > + - tsa-cell-id
> > + - '#address-cells'
> > + - '#size-cells'
> > + - '#chan-cells'
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/soc/fsl-tsa.h>
> > +
> > + scc_qmc@a60 {
>
> No underscores in node names.
>
> Node names should be generic.
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
Will be changed to qmc@a60
>
> > + compatible = "fsl,mpc885-scc-qmc", "fsl,cpm1-scc-qmc";
> > + reg = <0xa60 0x20>,
> > + <0x3f00 0xc0>,
> > + <0x2000 0x1000>;
> > + reg-names = "scc_regs", "scc_pram", "dpram";
> > + interrupts = <27>;
> > + interrupt-parent = <&CPM_PIC>;
> > + fsl,cpm-command = <0xc0>;
> > +
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + #chan-cells = <1>;
> > +
> > + tsa = <&tsa>;
> > + tsa-cell-id = <FSL_CPM_TSA_SCC4>;
> > +
> > + channel@16 {
> > + /* Ch16 : First 4 even TS from all routed from TSA */
> > + reg = <16>;
> > + fsl,mode = "transparent";
> > + fsl,reverse-data;
> > + tx-ts-mask = <0x00000000 0x000000AA>;
> > + rx-ts-mask = <0x00000000 0x000000AA>;
>
> Keep case consistent. lower-case hex.
Will be fixed
>
> Best regards,
> Krzysztof
>
Thanks for the review,
Best regards,
Hervé
--
Hervé Codina, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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