Add Ethernet controller node for mt8195.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 77 ++++++++++++++++
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 92 ++++++++++++++++++++
2 files changed, 169 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
index 4fbd99eb496a..6a48c135f0da 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
@@ -78,6 +78,23 @@ optee_reserved: optee@43200000 {
};
};
+ð {
+ phy-mode ="rgmii-id";
+ phy-handle = <ðernet_phy0>;
+ snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>;
+ snps,reset-delays-us = <0 10000 80000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <ð_default_pins>;
+ pinctrl-1 = <ð_sleep_pins>;
+ status = "okay";
+
+ mdio {
+ ethernet_phy0: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+ };
+};
+
&i2c6 {
clock-frequency = <400000>;
pinctrl-0 = <&i2c6_pins>;
@@ -258,6 +275,66 @@ &mt6359_vsram_others_ldo_reg {
};
&pio {
+ eth_default_pins: eth-default-pins {
+ pins-txd {
+ pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>,
+ <PINMUX_GPIO78__FUNC_GBE_TXD2>,
+ <PINMUX_GPIO79__FUNC_GBE_TXD1>,
+ <PINMUX_GPIO80__FUNC_GBE_TXD0>;
+ drive-strength = <MTK_DRIVE_8mA>;
+ };
+ pins-cc {
+ pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
+ <PINMUX_GPIO88__FUNC_GBE_TXEN>,
+ <PINMUX_GPIO87__FUNC_GBE_RXDV>,
+ <PINMUX_GPIO86__FUNC_GBE_RXC>;
+ drive-strength = <MTK_DRIVE_8mA>;
+ };
+ pins-rxd {
+ pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>,
+ <PINMUX_GPIO82__FUNC_GBE_RXD2>,
+ <PINMUX_GPIO83__FUNC_GBE_RXD1>,
+ <PINMUX_GPIO84__FUNC_GBE_RXD0>;
+ };
+ pins-mdio {
+ pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>,
+ <PINMUX_GPIO90__FUNC_GBE_MDIO>;
+ input-enable;
+ };
+ pins-power {
+ pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
+ <PINMUX_GPIO92__FUNC_GPIO92>;
+ output-high;
+ };
+ };
+
+ eth_sleep_pins: eth-sleep-pins {
+ pins-txd {
+ pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
+ <PINMUX_GPIO78__FUNC_GPIO78>,
+ <PINMUX_GPIO79__FUNC_GPIO79>,
+ <PINMUX_GPIO80__FUNC_GPIO80>;
+ };
+ pins-cc {
+ pinmux = <PINMUX_GPIO85__FUNC_GPIO85>,
+ <PINMUX_GPIO88__FUNC_GPIO88>,
+ <PINMUX_GPIO87__FUNC_GPIO87>,
+ <PINMUX_GPIO86__FUNC_GPIO86>;
+ };
+ pins-rxd {
+ pinmux = <PINMUX_GPIO81__FUNC_GPIO81>,
+ <PINMUX_GPIO82__FUNC_GPIO82>,
+ <PINMUX_GPIO83__FUNC_GPIO83>,
+ <PINMUX_GPIO84__FUNC_GPIO84>;
+ };
+ pins-mdio {
+ pinmux = <PINMUX_GPIO89__FUNC_GPIO89>,
+ <PINMUX_GPIO90__FUNC_GPIO90>;
+ input-disable;
+ bias-disable;
+ };
+ };
+
gpio_keys_pins: gpio-keys-pins {
pins {
pinmux = <PINMUX_GPIO106__FUNC_GPIO106>;
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 5d31536f4c48..28b3ebd145bf 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1046,6 +1046,98 @@ spis1: spi@1101e000 {
status = "disabled";
};
+ eth: ethernet@11021000 {
+ compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a";
+ reg = <0 0x11021000 0 0x4000>;
+ interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "macirq";
+ clock-names = "axi",
+ "apb",
+ "mac_main",
+ "ptp_ref",
+ "rmii_internal",
+ "mac_cg";
+ clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>,
+ <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>,
+ <&topckgen CLK_TOP_SNPS_ETH_250M>,
+ <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
+ <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>,
+ <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
+ assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
+ <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
+ <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>;
+ assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
+ <&topckgen CLK_TOP_ETHPLL_D8>,
+ <&topckgen CLK_TOP_ETHPLL_D10>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>;
+ mediatek,pericfg = <&infracfg_ao>;
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,mtl-rx-config = <&mtl_rx_setup>;
+ snps,mtl-tx-config = <&mtl_tx_setup>;
+ snps,txpbl = <16>;
+ snps,rxpbl = <16>;
+ snps,clk-csr = <0>;
+ status = "disabled";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ stmmac_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <0x7>;
+ snps,rd_osr_lmt = <0x7>;
+ snps,blen = <0 0 0 0 16 8 4>;
+ };
+
+ mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <4>;
+ snps,rx-sched-sp;
+ queue0 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ };
+ queue1 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ };
+ queue2 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ };
+ queue3 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ };
+ };
+
+ mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <4>;
+ snps,tx-sched-wrr;
+ queue0 {
+ snps,weight = <0x10>;
+ snps,dcb-algorithm;
+ snps,priority = <0x0>;
+ };
+ queue1 {
+ snps,weight = <0x11>;
+ snps,dcb-algorithm;
+ snps,priority = <0x1>;
+ };
+ queue2 {
+ snps,weight = <0x12>;
+ snps,dcb-algorithm;
+ snps,priority = <0x2>;
+ };
+ queue3 {
+ snps,weight = <0x13>;
+ snps,dcb-algorithm;
+ snps,priority = <0x3>;
+ };
+ };
+ };
+
xhci0: usb@11200000 {
compatible = "mediatek,mt8195-xhci",
"mediatek,mtk-xhci";
--
2.25.1
On 05/01/2023 02:07, Biao Huang wrote: > Add Ethernet controller node for mt8195. > > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > Reviewed-by: Andrew Lunn <andrew@lunn.ch> > Signed-off-by: Biao Huang <biao.huang@mediatek.com> Applied, thanks! > --- > arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 77 ++++++++++++++++ > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 92 ++++++++++++++++++++ > 2 files changed, 169 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts > index 4fbd99eb496a..6a48c135f0da 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts > +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts > @@ -78,6 +78,23 @@ optee_reserved: optee@43200000 { > }; > }; > > +ð { > + phy-mode ="rgmii-id"; > + phy-handle = <ðernet_phy0>; > + snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>; > + snps,reset-delays-us = <0 10000 80000>; > + pinctrl-names = "default", "sleep"; > + pinctrl-0 = <ð_default_pins>; > + pinctrl-1 = <ð_sleep_pins>; > + status = "okay"; > + > + mdio { > + ethernet_phy0: ethernet-phy@1 { > + reg = <0x1>; > + }; > + }; > +}; > + > &i2c6 { > clock-frequency = <400000>; > pinctrl-0 = <&i2c6_pins>; > @@ -258,6 +275,66 @@ &mt6359_vsram_others_ldo_reg { > }; > > &pio { > + eth_default_pins: eth-default-pins { > + pins-txd { > + pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>, > + <PINMUX_GPIO78__FUNC_GBE_TXD2>, > + <PINMUX_GPIO79__FUNC_GBE_TXD1>, > + <PINMUX_GPIO80__FUNC_GBE_TXD0>; > + drive-strength = <MTK_DRIVE_8mA>; > + }; > + pins-cc { > + pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>, > + <PINMUX_GPIO88__FUNC_GBE_TXEN>, > + <PINMUX_GPIO87__FUNC_GBE_RXDV>, > + <PINMUX_GPIO86__FUNC_GBE_RXC>; > + drive-strength = <MTK_DRIVE_8mA>; > + }; > + pins-rxd { > + pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>, > + <PINMUX_GPIO82__FUNC_GBE_RXD2>, > + <PINMUX_GPIO83__FUNC_GBE_RXD1>, > + <PINMUX_GPIO84__FUNC_GBE_RXD0>; > + }; > + pins-mdio { > + pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>, > + <PINMUX_GPIO90__FUNC_GBE_MDIO>; > + input-enable; > + }; > + pins-power { > + pinmux = <PINMUX_GPIO91__FUNC_GPIO91>, > + <PINMUX_GPIO92__FUNC_GPIO92>; > + output-high; > + }; > + }; > + > + eth_sleep_pins: eth-sleep-pins { > + pins-txd { > + pinmux = <PINMUX_GPIO77__FUNC_GPIO77>, > + <PINMUX_GPIO78__FUNC_GPIO78>, > + <PINMUX_GPIO79__FUNC_GPIO79>, > + <PINMUX_GPIO80__FUNC_GPIO80>; > + }; > + pins-cc { > + pinmux = <PINMUX_GPIO85__FUNC_GPIO85>, > + <PINMUX_GPIO88__FUNC_GPIO88>, > + <PINMUX_GPIO87__FUNC_GPIO87>, > + <PINMUX_GPIO86__FUNC_GPIO86>; > + }; > + pins-rxd { > + pinmux = <PINMUX_GPIO81__FUNC_GPIO81>, > + <PINMUX_GPIO82__FUNC_GPIO82>, > + <PINMUX_GPIO83__FUNC_GPIO83>, > + <PINMUX_GPIO84__FUNC_GPIO84>; > + }; > + pins-mdio { > + pinmux = <PINMUX_GPIO89__FUNC_GPIO89>, > + <PINMUX_GPIO90__FUNC_GPIO90>; > + input-disable; > + bias-disable; > + }; > + }; > + > gpio_keys_pins: gpio-keys-pins { > pins { > pinmux = <PINMUX_GPIO106__FUNC_GPIO106>; > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > index 5d31536f4c48..28b3ebd145bf 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > @@ -1046,6 +1046,98 @@ spis1: spi@1101e000 { > status = "disabled"; > }; > > + eth: ethernet@11021000 { > + compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a"; > + reg = <0 0x11021000 0 0x4000>; > + interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>; > + interrupt-names = "macirq"; > + clock-names = "axi", > + "apb", > + "mac_main", > + "ptp_ref", > + "rmii_internal", > + "mac_cg"; > + clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>, > + <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, > + <&topckgen CLK_TOP_SNPS_ETH_250M>, > + <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, > + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>, > + <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; > + assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>, > + <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, > + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; > + assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>, > + <&topckgen CLK_TOP_ETHPLL_D8>, > + <&topckgen CLK_TOP_ETHPLL_D10>; > + power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>; > + mediatek,pericfg = <&infracfg_ao>; > + snps,axi-config = <&stmmac_axi_setup>; > + snps,mtl-rx-config = <&mtl_rx_setup>; > + snps,mtl-tx-config = <&mtl_tx_setup>; > + snps,txpbl = <16>; > + snps,rxpbl = <16>; > + snps,clk-csr = <0>; > + status = "disabled"; > + > + mdio { > + compatible = "snps,dwmac-mdio"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + stmmac_axi_setup: stmmac-axi-config { > + snps,wr_osr_lmt = <0x7>; > + snps,rd_osr_lmt = <0x7>; > + snps,blen = <0 0 0 0 16 8 4>; > + }; > + > + mtl_rx_setup: rx-queues-config { > + snps,rx-queues-to-use = <4>; > + snps,rx-sched-sp; > + queue0 { > + snps,dcb-algorithm; > + snps,map-to-dma-channel = <0x0>; > + }; > + queue1 { > + snps,dcb-algorithm; > + snps,map-to-dma-channel = <0x0>; > + }; > + queue2 { > + snps,dcb-algorithm; > + snps,map-to-dma-channel = <0x0>; > + }; > + queue3 { > + snps,dcb-algorithm; > + snps,map-to-dma-channel = <0x0>; > + }; > + }; > + > + mtl_tx_setup: tx-queues-config { > + snps,tx-queues-to-use = <4>; > + snps,tx-sched-wrr; > + queue0 { > + snps,weight = <0x10>; > + snps,dcb-algorithm; > + snps,priority = <0x0>; > + }; > + queue1 { > + snps,weight = <0x11>; > + snps,dcb-algorithm; > + snps,priority = <0x1>; > + }; > + queue2 { > + snps,weight = <0x12>; > + snps,dcb-algorithm; > + snps,priority = <0x2>; > + }; > + queue3 { > + snps,weight = <0x13>; > + snps,dcb-algorithm; > + snps,priority = <0x3>; > + }; > + }; > + }; > + > xhci0: usb@11200000 { > compatible = "mediatek,mt8195-xhci", > "mediatek,mtk-xhci";
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