The RISC-V AIA specification improves handling per-HART local interrupts
in a backward compatible manner. This patch adds defines for new RISC-V
AIA CSRs.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
arch/riscv/include/asm/csr.h | 92 ++++++++++++++++++++++++++++++++++++
1 file changed, 92 insertions(+)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 0e571f6483d9..4e1356bad7b2 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -73,7 +73,10 @@
#define IRQ_S_EXT 9
#define IRQ_VS_EXT 10
#define IRQ_M_EXT 11
+#define IRQ_S_GEXT 12
#define IRQ_PMU_OVF 13
+#define IRQ_LOCAL_MAX (IRQ_PMU_OVF + 1)
+#define IRQ_LOCAL_MASK ((_AC(1, UL) << IRQ_LOCAL_MAX) - 1)
/* Exception causes */
#define EXC_INST_MISALIGNED 0
@@ -156,6 +159,26 @@
(_AC(1, UL) << IRQ_S_TIMER) | \
(_AC(1, UL) << IRQ_S_EXT))
+/* AIA CSR bits */
+#define TOPI_IID_SHIFT 16
+#define TOPI_IID_MASK 0xfff
+#define TOPI_IPRIO_MASK 0xff
+#define TOPI_IPRIO_BITS 8
+
+#define TOPEI_ID_SHIFT 16
+#define TOPEI_ID_MASK 0x7ff
+#define TOPEI_PRIO_MASK 0x7ff
+
+#define ISELECT_IPRIO0 0x30
+#define ISELECT_IPRIO15 0x3f
+#define ISELECT_MASK 0x1ff
+
+#define HVICTL_VTI 0x40000000
+#define HVICTL_IID 0x0fff0000
+#define HVICTL_IID_SHIFT 16
+#define HVICTL_IPRIOM 0x00000100
+#define HVICTL_IPRIO 0x000000ff
+
/* xENVCFG flags */
#define ENVCFG_STCE (_AC(1, ULL) << 63)
#define ENVCFG_PBMTE (_AC(1, ULL) << 62)
@@ -250,6 +273,18 @@
#define CSR_STIMECMP 0x14D
#define CSR_STIMECMPH 0x15D
+/* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
+#define CSR_SISELECT 0x150
+#define CSR_SIREG 0x151
+
+/* Supervisor-Level Interrupts (AIA) */
+#define CSR_STOPEI 0x15c
+#define CSR_STOPI 0xdb0
+
+/* Supervisor-Level High-Half CSRs (AIA) */
+#define CSR_SIEH 0x114
+#define CSR_SIPH 0x154
+
#define CSR_VSSTATUS 0x200
#define CSR_VSIE 0x204
#define CSR_VSTVEC 0x205
@@ -279,8 +314,32 @@
#define CSR_HGATP 0x680
#define CSR_HGEIP 0xe12
+/* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
+#define CSR_HVIEN 0x608
+#define CSR_HVICTL 0x609
+#define CSR_HVIPRIO1 0x646
+#define CSR_HVIPRIO2 0x647
+
+/* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */
+#define CSR_VSISELECT 0x250
+#define CSR_VSIREG 0x251
+
+/* VS-Level Interrupts (H-extension with AIA) */
+#define CSR_VSTOPEI 0x25c
+#define CSR_VSTOPI 0xeb0
+
+/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
+#define CSR_HIDELEGH 0x613
+#define CSR_HVIENH 0x618
+#define CSR_HVIPH 0x655
+#define CSR_HVIPRIO1H 0x656
+#define CSR_HVIPRIO2H 0x657
+#define CSR_VSIEH 0x214
+#define CSR_VSIPH 0x254
+
#define CSR_MSTATUS 0x300
#define CSR_MISA 0x301
+#define CSR_MIDELEG 0x303
#define CSR_MIE 0x304
#define CSR_MTVEC 0x305
#define CSR_MENVCFG 0x30a
@@ -297,6 +356,25 @@
#define CSR_MIMPID 0xf13
#define CSR_MHARTID 0xf14
+/* Machine-Level Window to Indirectly Accessed Registers (AIA) */
+#define CSR_MISELECT 0x350
+#define CSR_MIREG 0x351
+
+/* Machine-Level Interrupts (AIA) */
+#define CSR_MTOPEI 0x35c
+#define CSR_MTOPI 0xfb0
+
+/* Virtual Interrupts for Supervisor Level (AIA) */
+#define CSR_MVIEN 0x308
+#define CSR_MVIP 0x309
+
+/* Machine-Level High-Half CSRs (AIA) */
+#define CSR_MIDELEGH 0x313
+#define CSR_MIEH 0x314
+#define CSR_MVIENH 0x318
+#define CSR_MVIPH 0x319
+#define CSR_MIPH 0x354
+
#ifdef CONFIG_RISCV_M_MODE
# define CSR_STATUS CSR_MSTATUS
# define CSR_IE CSR_MIE
@@ -307,6 +385,13 @@
# define CSR_TVAL CSR_MTVAL
# define CSR_IP CSR_MIP
+# define CSR_IEH CSR_MIEH
+# define CSR_ISELECT CSR_MISELECT
+# define CSR_IREG CSR_MIREG
+# define CSR_IPH CSR_MIPH
+# define CSR_TOPEI CSR_MTOPEI
+# define CSR_TOPI CSR_MTOPI
+
# define SR_IE SR_MIE
# define SR_PIE SR_MPIE
# define SR_PP SR_MPP
@@ -324,6 +409,13 @@
# define CSR_TVAL CSR_STVAL
# define CSR_IP CSR_SIP
+# define CSR_IEH CSR_SIEH
+# define CSR_ISELECT CSR_SISELECT
+# define CSR_IREG CSR_SIREG
+# define CSR_IPH CSR_SIPH
+# define CSR_TOPEI CSR_STOPEI
+# define CSR_TOPI CSR_STOPI
+
# define SR_IE SR_SIE
# define SR_PIE SR_SPIE
# define SR_PP SR_SPP
--
2.34.1Hey Anup! On Tue, Jan 03, 2023 at 07:44:01PM +0530, Anup Patel wrote: > The RISC-V AIA specification improves handling per-HART local interrupts > in a backward compatible manner. This patch adds defines for new RISC-V > AIA CSRs. > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > --- > arch/riscv/include/asm/csr.h | 92 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 92 insertions(+) > > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h > index 0e571f6483d9..4e1356bad7b2 100644 > --- a/arch/riscv/include/asm/csr.h > +++ b/arch/riscv/include/asm/csr.h > @@ -73,7 +73,10 @@ > #define IRQ_S_EXT 9 > #define IRQ_VS_EXT 10 > #define IRQ_M_EXT 11 > +#define IRQ_S_GEXT 12 > #define IRQ_PMU_OVF 13 > +#define IRQ_LOCAL_MAX (IRQ_PMU_OVF + 1) > +#define IRQ_LOCAL_MASK ((_AC(1, UL) << IRQ_LOCAL_MAX) - 1) > > /* Exception causes */ > #define EXC_INST_MISALIGNED 0 > @@ -156,6 +159,26 @@ > (_AC(1, UL) << IRQ_S_TIMER) | \ > (_AC(1, UL) << IRQ_S_EXT)) > > +/* AIA CSR bits */ > +#define TOPI_IID_SHIFT 16 > +#define TOPI_IID_MASK 0xfff > +#define TOPI_IPRIO_MASK 0xff > +#define TOPI_IPRIO_BITS 8 > + > +#define TOPEI_ID_SHIFT 16 > +#define TOPEI_ID_MASK 0x7ff > +#define TOPEI_PRIO_MASK 0x7ff > + > +#define ISELECT_IPRIO0 0x30 > +#define ISELECT_IPRIO15 0x3f > +#define ISELECT_MASK 0x1ff > + > +#define HVICTL_VTI 0x40000000 > +#define HVICTL_IID 0x0fff0000 > +#define HVICTL_IID_SHIFT 16 > +#define HVICTL_IPRIOM 0x00000100 > +#define HVICTL_IPRIO 0x000000ff Why not name these as masks, like you did for the other masks? Also, the mask/shift defines appear inconsistent. TOPI_IID_MASK is intended to be used post-shift AFAICT, but HVICTL_IID_SHIFT is intended to be used *pre*-shift. Some consistency in naming and function would be great. > +/* Machine-Level High-Half CSRs (AIA) */ > +#define CSR_MIDELEGH 0x313 I feel like I could find Midelegh in an Irish dictionary lol Anyways, I went through the CSRs and they do all seem correct. Thanks, Conor.
On Thu, Jan 5, 2023 at 4:37 AM Conor Dooley <conor@kernel.org> wrote: > > Hey Anup! > > On Tue, Jan 03, 2023 at 07:44:01PM +0530, Anup Patel wrote: > > The RISC-V AIA specification improves handling per-HART local interrupts > > in a backward compatible manner. This patch adds defines for new RISC-V > > AIA CSRs. > > > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > > --- > > arch/riscv/include/asm/csr.h | 92 ++++++++++++++++++++++++++++++++++++ > > 1 file changed, 92 insertions(+) > > > > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h > > index 0e571f6483d9..4e1356bad7b2 100644 > > --- a/arch/riscv/include/asm/csr.h > > +++ b/arch/riscv/include/asm/csr.h > > @@ -73,7 +73,10 @@ > > #define IRQ_S_EXT 9 > > #define IRQ_VS_EXT 10 > > #define IRQ_M_EXT 11 > > +#define IRQ_S_GEXT 12 > > #define IRQ_PMU_OVF 13 > > +#define IRQ_LOCAL_MAX (IRQ_PMU_OVF + 1) > > +#define IRQ_LOCAL_MASK ((_AC(1, UL) << IRQ_LOCAL_MAX) - 1) > > > > /* Exception causes */ > > #define EXC_INST_MISALIGNED 0 > > @@ -156,6 +159,26 @@ > > (_AC(1, UL) << IRQ_S_TIMER) | \ > > (_AC(1, UL) << IRQ_S_EXT)) > > > > +/* AIA CSR bits */ > > +#define TOPI_IID_SHIFT 16 > > +#define TOPI_IID_MASK 0xfff > > +#define TOPI_IPRIO_MASK 0xff > > +#define TOPI_IPRIO_BITS 8 > > + > > +#define TOPEI_ID_SHIFT 16 > > +#define TOPEI_ID_MASK 0x7ff > > +#define TOPEI_PRIO_MASK 0x7ff > > + > > +#define ISELECT_IPRIO0 0x30 > > +#define ISELECT_IPRIO15 0x3f > > +#define ISELECT_MASK 0x1ff > > + > > +#define HVICTL_VTI 0x40000000 > > +#define HVICTL_IID 0x0fff0000 > > +#define HVICTL_IID_SHIFT 16 > > +#define HVICTL_IPRIOM 0x00000100 > > +#define HVICTL_IPRIO 0x000000ff > > Why not name these as masks, like you did for the other masks? > Also, the mask/shift defines appear inconsistent. TOPI_IID_MASK is > intended to be used post-shift AFAICT, but HVICTL_IID_SHIFT is intended > to be used *pre*-shift. > Some consistency in naming and function would be great. The following convention is being followed in asm/csr.h for defining MASK of any XYZ field in ABC CSR: 1. ABC_XYZ : This name is used for MASK which is intended to be used before SHIFT 2. ABC_XYZ_MASK: This name is used for MASK which is intended to be used after SHIFT The existing defines for [M|S]STATUS, HSTATUS, SATP, and xENVCFG follows the above convention. The only outlier is HGATPx_VMID_MASK define which I will fix in my next KVM RISC-V series. I don't see how any of the AIA CSR defines are violating the above convention. The choice of ABC_XYZ versus ABC_XYZ_MASK name is upto the developer as long as the above convention is not violated. > > > > +/* Machine-Level High-Half CSRs (AIA) */ > > +#define CSR_MIDELEGH 0x313 > > I feel like I could find Midelegh in an Irish dictionary lol > Anyways, I went through the CSRs and they do all seem correct. > > Thanks, > Conor. > > Regards, Anup
Hey Anup, I thought I had already replied here but clearly not, sorry! On Mon, Jan 09, 2023 at 10:39:08AM +0530, Anup Patel wrote: > On Thu, Jan 5, 2023 at 4:37 AM Conor Dooley <conor@kernel.org> wrote: > > On Tue, Jan 03, 2023 at 07:44:01PM +0530, Anup Patel wrote: > > > +/* AIA CSR bits */ > > > +#define TOPI_IID_SHIFT 16 > > > +#define TOPI_IID_MASK 0xfff While I think of it, it'd be worth noting that these are generic across all of topi, mtopi etc. Initially I thought that this mask was wrong as the topi section says: bits 25:16 Interrupt identity (source number) bits 7:0 Interrupt priority > > > +#define TOPI_IPRIO_MASK 0xff > > > +#define TOPI_IPRIO_BITS 8 > > > + > > > +#define TOPEI_ID_SHIFT 16 > > > +#define TOPEI_ID_MASK 0x7ff > > > +#define TOPEI_PRIO_MASK 0x7ff > > > + > > > +#define ISELECT_IPRIO0 0x30 > > > +#define ISELECT_IPRIO15 0x3f > > > +#define ISELECT_MASK 0x1ff > > > + > > > +#define HVICTL_VTI 0x40000000 > > > +#define HVICTL_IID 0x0fff0000 > > > +#define HVICTL_IID_SHIFT 16 > > > +#define HVICTL_IPRIOM 0x00000100 > > > +#define HVICTL_IPRIO 0x000000ff > > > > Why not name these as masks, like you did for the other masks? > > Also, the mask/shift defines appear inconsistent. TOPI_IID_MASK is > > intended to be used post-shift AFAICT, but HVICTL_IID_SHIFT is intended > > to be used *pre*-shift. > > Some consistency in naming and function would be great. > > The following convention is being followed in asm/csr.h for defining > MASK of any XYZ field in ABC CSR: > 1. ABC_XYZ : This name is used for MASK which is intended > to be used before SHIFT > 2. ABC_XYZ_MASK: This name is used for MASK which is > intended to be used after SHIFT Which makes sense in theory. > The existing defines for [M|S]STATUS, HSTATUS, SATP, and xENVCFG > follows the above convention. The only outlier is HGATPx_VMID_MASK > define which I will fix in my next KVM RISC-V series. Yup, it is liable to end up like that. > I don't see how any of the AIA CSR defines are violating the above > convention. What I was advocating for was picking one style and sticking to it. These copy-paste from docs things are tedious and error prone to review, and I don't think having multiple styles is helpful. Tedious as it was, I did check all the numbers though, so in that respect: Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Thanks, Conor.
On Wed, Jan 18, 2023 at 2:12 AM Conor Dooley <conor@kernel.org> wrote:
>
> Hey Anup,
>
> I thought I had already replied here but clearly not, sorry!
>
> On Mon, Jan 09, 2023 at 10:39:08AM +0530, Anup Patel wrote:
> > On Thu, Jan 5, 2023 at 4:37 AM Conor Dooley <conor@kernel.org> wrote:
> > > On Tue, Jan 03, 2023 at 07:44:01PM +0530, Anup Patel wrote:
>
> > > > +/* AIA CSR bits */
> > > > +#define TOPI_IID_SHIFT 16
> > > > +#define TOPI_IID_MASK 0xfff
>
> While I think of it, it'd be worth noting that these are generic across
> all of topi, mtopi etc. Initially I thought that this mask was wrong as
> the topi section says:
> bits 25:16 Interrupt identity (source number)
> bits 7:0 Interrupt priority
These defines are for the AIA CSRs and not AIA APLIC IDC registers.
As per the latest frozen spec, the mtopi/stopi/vstopi has following bits:
bits: 27:16 IID
bits: 7:0 IPRIO
>
> > > > +#define TOPI_IPRIO_MASK 0xff
> > > > +#define TOPI_IPRIO_BITS 8
> > > > +
> > > > +#define TOPEI_ID_SHIFT 16
> > > > +#define TOPEI_ID_MASK 0x7ff
> > > > +#define TOPEI_PRIO_MASK 0x7ff
> > > > +
> > > > +#define ISELECT_IPRIO0 0x30
> > > > +#define ISELECT_IPRIO15 0x3f
> > > > +#define ISELECT_MASK 0x1ff
> > > > +
> > > > +#define HVICTL_VTI 0x40000000
> > > > +#define HVICTL_IID 0x0fff0000
> > > > +#define HVICTL_IID_SHIFT 16
> > > > +#define HVICTL_IPRIOM 0x00000100
> > > > +#define HVICTL_IPRIO 0x000000ff
> > >
> > > Why not name these as masks, like you did for the other masks?
> > > Also, the mask/shift defines appear inconsistent. TOPI_IID_MASK is
> > > intended to be used post-shift AFAICT, but HVICTL_IID_SHIFT is intended
> > > to be used *pre*-shift.
> > > Some consistency in naming and function would be great.
> >
> > The following convention is being followed in asm/csr.h for defining
> > MASK of any XYZ field in ABC CSR:
> > 1. ABC_XYZ : This name is used for MASK which is intended
> > to be used before SHIFT
> > 2. ABC_XYZ_MASK: This name is used for MASK which is
> > intended to be used after SHIFT
>
> Which makes sense in theory.
>
> > The existing defines for [M|S]STATUS, HSTATUS, SATP, and xENVCFG
> > follows the above convention. The only outlier is HGATPx_VMID_MASK
> > define which I will fix in my next KVM RISC-V series.
>
> Yup, it is liable to end up like that.
>
> > I don't see how any of the AIA CSR defines are violating the above
> > convention.
>
> What I was advocating for was picking one style and sticking to it.
> These copy-paste from docs things are tedious and error prone to review,
> and I don't think having multiple styles is helpful.
On the other hand, I think we should let developers choose a style
which is better suited for a particular register field instead enforcing
it here. The best we can do is follow a naming convention for defines.
>
> Tedious as it was, I did check all the numbers though, so in that
> respect:
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
BTW, this patch is shared with KVM AIA CSR series so most likely
I will take this patch through that series.
Regards,
Anup
On Fri, Jan 27, 2023 at 05:28:57PM +0530, Anup Patel wrote: > On Wed, Jan 18, 2023 at 2:12 AM Conor Dooley <conor@kernel.org> wrote: > > > > > +/* AIA CSR bits */ > > > > > +#define TOPI_IID_SHIFT 16 > > > > > +#define TOPI_IID_MASK 0xfff > > > > While I think of it, it'd be worth noting that these are generic across > > all of topi, mtopi etc. Initially I thought that this mask was wrong as > > the topi section says: > > bits 25:16 Interrupt identity (source number) > > bits 7:0 Interrupt priority > > These defines are for the AIA CSRs and not AIA APLIC IDC registers. > > As per the latest frozen spec, the mtopi/stopi/vstopi has following bits: > bits: 27:16 IID > bits: 7:0 IPRIO I know, that those ones use those bits, hence leaving an R-b for the patch - but your define says TOPI, which it is *not* accurate for. That is confusing and should be noted. > > What I was advocating for was picking one style and sticking to it. > > These copy-paste from docs things are tedious and error prone to review, > > and I don't think having multiple styles is helpful. > > On the other hand, I think we should let developers choose a style > which is better suited for a particular register field instead enforcing > it here. The best we can do is follow a naming convention for defines. Well shall have to agree to disagree I suppose! > > Tedious as it was, I did check all the numbers though, so in that > > respect: > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > BTW, this patch is shared with KVM AIA CSR series so most likely > I will take this patch through that series. Since the path which it gets applied is between you and Palmer to decide, feel free to add the R-b whichever way the patch ends up going! Thanks, Conor.
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