The "mediatek,mt8192-scp_adsp" binding requires a power domain to be
specified.

Fixes: 4a803990aeb1 ("dt-bindings: ARM: Mediatek: Add new document bindings of MT8192 clock")
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 .../arm/mediatek/mediatek,mt8192-clock.yaml     | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
index b57cc2e69efb..ce8dd2bfb533 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
@@ -40,6 +40,9 @@ properties:
   reg:
     maxItems: 1
 
+  power-domains:
+    maxItems: 1
+
   '#clock-cells':
     const: 1
 
@@ -47,13 +50,27 @@ required:
   - compatible
   - reg
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - mediatek,mt8192-scp_adsp
+    then:
+      required:
+        - power-domains
+
 additionalProperties: false
 
 examples:
   - |
+    #include <dt-bindings/power/mt8192-power.h>
+
     scp_adsp: clock-controller@10720000 {
         compatible = "mediatek,mt8192-scp_adsp";
         reg = <0x10720000 0x1000>;
+        power-domains = <&spm MT8192_POWER_DOMAIN_ADSP>;
         #clock-cells = <1>;
     };
 
-- 
2.18.0

Il 21/12/22 04:44, Allen-KH Cheng ha scritto:
> The "mediatek,mt8192-scp_adsp" binding requires a power domain to be
> specified.
> 
> Fixes: 4a803990aeb1 ("dt-bindings: ARM: Mediatek: Add new document bindings of MT8192 clock")
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
>   .../arm/mediatek/mediatek,mt8192-clock.yaml     | 17 +++++++++++++++++
>   1 file changed, 17 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
> index b57cc2e69efb..ce8dd2bfb533 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
> @@ -40,6 +40,9 @@ properties:
>     reg:
>       maxItems: 1
>   
> +  power-domains:
> +    maxItems: 1
> +
>     '#clock-cells':
>       const: 1
>   
> @@ -47,13 +50,27 @@ required:
>     - compatible
>     - reg
>   
> +allOf:

allOf is unnecessary here.

Regards,
Angelo

On 21/12/2022 11:22, AngeloGioacchino Del Regno wrote:
> Il 21/12/22 04:44, Allen-KH Cheng ha scritto:
>> The "mediatek,mt8192-scp_adsp" binding requires a power domain to be
>> specified.
>>
>> Fixes: 4a803990aeb1 ("dt-bindings: ARM: Mediatek: Add new document bindings of MT8192 clock")
>> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
>> ---
>>   .../arm/mediatek/mediatek,mt8192-clock.yaml     | 17 +++++++++++++++++
>>   1 file changed, 17 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
>> index b57cc2e69efb..ce8dd2bfb533 100644
>> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
>> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
>> @@ -40,6 +40,9 @@ properties:
>>     reg:
>>       maxItems: 1
>>   
>> +  power-domains:
>> +    maxItems: 1
>> +
>>     '#clock-cells':
>>       const: 1
>>   
>> @@ -47,13 +50,27 @@ required:
>>     - compatible
>>     - reg
>>   
>> +allOf:
> 
> allOf is unnecessary here.

If you mean that "if:" can be without it, then it is better to have
allOf. It grows often, so you avoid useless indentation change later.


Best regards,
Krzysztof

Il 21/12/22 11:33, Krzysztof Kozlowski ha scritto:
> On 21/12/2022 11:22, AngeloGioacchino Del Regno wrote:
>> Il 21/12/22 04:44, Allen-KH Cheng ha scritto:
>>> The "mediatek,mt8192-scp_adsp" binding requires a power domain to be
>>> specified.
>>>
>>> Fixes: 4a803990aeb1 ("dt-bindings: ARM: Mediatek: Add new document bindings of MT8192 clock")
>>> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
>>> ---
>>>    .../arm/mediatek/mediatek,mt8192-clock.yaml     | 17 +++++++++++++++++
>>>    1 file changed, 17 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
>>> index b57cc2e69efb..ce8dd2bfb533 100644
>>> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
>>> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
>>> @@ -40,6 +40,9 @@ properties:
>>>      reg:
>>>        maxItems: 1
>>>    
>>> +  power-domains:
>>> +    maxItems: 1
>>> +
>>>      '#clock-cells':
>>>        const: 1
>>>    
>>> @@ -47,13 +50,27 @@ required:
>>>      - compatible
>>>      - reg
>>>    
>>> +allOf:
>>
>> allOf is unnecessary here.
> 
> If you mean that "if:" can be without it, then it is better to have
> allOf. It grows often, so you avoid useless indentation change later.
> 
> 

Yes, that's what I mean. I've suggested so because I don't expect this list
to grow in the future.

Regards,
Angelo

On 21/12/2022 04:44, Allen-KH Cheng wrote:
> The "mediatek,mt8192-scp_adsp" binding requires a power domain to be
> specified.

That's not true. Before this patch, how does the binding require a power
domain? Please show me the part of binding which requires it.

Best regards,
Krzysztof

On Wed, Dec 21, 2022 at 4:18 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 21/12/2022 04:44, Allen-KH Cheng wrote:
> > The "mediatek,mt8192-scp_adsp" binding requires a power domain to be
> > specified.
>
> That's not true. Before this patch, how does the binding require a power
> domain? Please show me the part of binding which requires it.

Maybe this should be reworded to something like the following?

<--- cut
The SCP_ADSP clock controller has a power domain dependency that was not
described properly. Add it to the binding.
<--- cut

This was discovered when I was reworking the clock drivers. The clocks
in this controller were being turned off by the clock core, which would
result in the system locking up. MediaTek said this was due to the power
domain.

Regards
ChenYu