AC5 SoC has Xenon SDHCI IP, but with a limitation of maximum
2G DMA address range.

Signed-off-by: Vadym Kochan <vadym.kochan@plvision.eu>
---
v3:
   #1 Put compatible string in alphabetical order in the yaml file

 Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml
index 3ee758886558..3546de114d7c 100644
--- a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml
+++ b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml
@@ -23,6 +23,7 @@ properties:
   compatible:
     oneOf:
       - enum:
+          - marvell,ac5-sdhci
           - marvell,armada-cp110-sdhci
           - marvell,armada-ap806-sdhci
 
-- 
2.25.1

On 05/12/2022 11:59, Vadym Kochan wrote:
> AC5 SoC has Xenon SDHCI IP, but with a limitation of maximum
> 2G DMA address range.
> 
> Signed-off-by: Vadym Kochan <vadym.kochan@plvision.eu>
> ---
> v3:
>    #1 Put compatible string in alphabetical order in the yaml file
> 

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof