Hi Joerg,

Below fixes are queued for v6.1. They aim to fix:

- Preset Access bit in FL non-leaf paging entries.
- Avoid setting hardware Reserved(0) bit.

This series is also available at github.
https://github.com/LuBaolu/intel-iommu/commits/vtd-fix-for-v6.1-rc6

Please consider it for the iommu/fix branch.

Best regards,
Lu Baolu

Tina Zhang (2):
  iommu/vt-d: Preset Access bit for IOVA in FL non-leaf paging entries
  iommu/vt-d: Set SRE bit only when hardware has SRS cap

 drivers/iommu/intel/iommu.c | 8 +++-----
 drivers/iommu/intel/pasid.c | 5 +++--
 2 files changed, 6 insertions(+), 7 deletions(-)

-- 
2.34.1

On Wed, Nov 16, 2022 at 01:15:42PM +0800, Lu Baolu wrote:
> Tina Zhang (2):
>   iommu/vt-d: Preset Access bit for IOVA in FL non-leaf paging entries
>   iommu/vt-d: Set SRE bit only when hardware has SRS cap
> 
>  drivers/iommu/intel/iommu.c | 8 +++-----
>  drivers/iommu/intel/pasid.c | 5 +++--
>  2 files changed, 6 insertions(+), 7 deletions(-)

Applied for v6.1, thanks Baolu and Tina.