Add the node for SA2UL for supporting hardware crypto algorithms,
including SHA1, SHA256, SHA512, AES, 3DES and AEAD suites.
Add rng node for hardware random number generator.

Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Acked-by: Matt Ranostay <mranostay@ti.com>
Acked-by: Andrew Davis <afd@ti.com>
---

Changes have been tested on local j721s2-evm board. Tcrypt tests
and crypto self-tests were passing.

Changelog v2 -> v3:
- remove the clock property from rng node
  (<https://lore.kernel.org/all/20220901171041.32056-1-afd@ti.com/>)

Changelog v1 -> v2:
- change the TI_SCI flag from shared to exclusive as OP-TEE uses MCU
  domain SA2UL instance and not the main domain instance
- remove the 'dma-coherent' property (Binding changes are merged)
- add the rng node which can be used as well for hwrng along with
  optee-rng

v2 patch: https://lore.kernel.org/all/20221031135416.350010-1-j-choudhary@ti.com/  

Testing log: https://gist.github.com/Jayesh2000/26acf0e63f7edcd4b267122e4c73b9a8

 arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index d1ec26110376..2e0ba2262e77 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -72,6 +72,25 @@ main_pmx0: pinctrl@11c000 {
 		pinctrl-single,function-mask = <0xffffffff>;
 	};
 
+	main_crypto: crypto@4e00000 {
+		compatible = "ti,j721e-sa2ul";
+		reg = <0x00 0x4e00000 0x00 0x1200>;
+		power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>;
+
+		dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>,
+				<&main_udmap 0x4a41>;
+		dma-names = "tx", "rx1", "rx2";
+
+		rng: rng@4e10000 {
+			compatible = "inside-secure,safexcel-eip76";
+			reg = <0x0 0x4e10000 0x0 0x7d>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+		};
+	};
+
 	main_uart0: serial@2800000 {
 		compatible = "ti,j721e-uart", "ti,am654-uart";
 		reg = <0x00 0x02800000 0x00 0x200>;
-- 
2.25.1

Hi Jayesh Choudhary,

On Tue, 1 Nov 2022 01:36:33 +0530, Jayesh Choudhary wrote:
> Add the node for SA2UL for supporting hardware crypto algorithms,
> including SHA1, SHA256, SHA512, AES, 3DES and AEAD suites.
> Add rng node for hardware random number generator.
> 
> 

I have applied the following to branch ti-k3-dts-next on [1].
Thank you!

For the next time around:
Maintain consistent formatting 0x%08x for addresses, formatting to line
things up etc. I have manually edited to do that for this time.

[1/1] arm64: dts: ti: k3-j721s2-main: Enable crypto accelerator
      commit: 027b85ca972f321629af85793bb49d45382e9006

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

[1] git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

On 01/11/22 01:36, Jayesh Choudhary wrote:
> Add the node for SA2UL for supporting hardware crypto algorithms,
> including SHA1, SHA256, SHA512, AES, 3DES and AEAD suites.
> Add rng node for hardware random number generator.
>
> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
> Acked-by: Matt Ranostay <mranostay@ti.com>
> Acked-by: Andrew Davis <afd@ti.com>
> ---
>
> Changes have been tested on local j721s2-evm board. Tcrypt tests
> and crypto self-tests were passing.
>
> Changelog v2 -> v3:
> - remove the clock property from rng node
>    (<https://lore.kernel.org/all/20220901171041.32056-1-afd@ti.com/>)
>
> Changelog v1 -> v2:
> - change the TI_SCI flag from shared to exclusive as OP-TEE uses MCU
>    domain SA2UL instance and not the main domain instance
> - remove the 'dma-coherent' property (Binding changes are merged)
> - add the rng node which can be used as well for hwrng along with
>    optee-rng
>
> v2 patch: https://lore.kernel.org/all/20221031135416.350010-1-j-choudhary@ti.com/
>
> Testing log: https://gist.github.com/Jayesh2000/26acf0e63f7edcd4b267122e4c73b9a8
>
>   arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 19 +++++++++++++++++++
>   1 file changed, 19 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> index d1ec26110376..2e0ba2262e77 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> @@ -72,6 +72,25 @@ main_pmx0: pinctrl@11c000 {
>   		pinctrl-single,function-mask = <0xffffffff>;
>   	};
>   
> +	main_crypto: crypto@4e00000 {
> +		compatible = "ti,j721e-sa2ul";
> +		reg = <0x00 0x4e00000 0x00 0x1200>;
> +		power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>;
> +
> +		dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>,
> +				<&main_udmap 0x4a41>;
> +		dma-names = "tx", "rx1", "rx2";
> +
> +		rng: rng@4e10000 {
> +			compatible = "inside-secure,safexcel-eip76";
> +			reg = <0x0 0x4e10000 0x0 0x7d>;
> +			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +	};
> +

Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>

>   	main_uart0: serial@2800000 {
>   		compatible = "ti,j721e-uart", "ti,am654-uart";
>   		reg = <0x00 0x02800000 0x00 0x200>;