When RX strap in HW is not set to MODE 3 or 4, bit 7 and 8 in CF4
register should be set. The former is already handled in
dp83867_config_init; add the latter in SGMII specific initialization.

Signed-off-by: Harini Katakam <harini.katakam@amd.com>
---
 drivers/net/phy/dp83867.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index 6939563d3b7c..a2aac9032af6 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -853,6 +853,13 @@ static int dp83867_config_init(struct phy_device *phydev)
 		else
 			val &= ~DP83867_SGMII_TYPE;
 		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
+		/* This is a SW workaround for link instability if RX_CTRL is
+		 * not strapped to mode 3 or 4 in HW. This is required for SGMII
+		 * in addition to clearing bit 7, handled above.
+		 */
+		if (dp83867->rxctrl_strap_quirk)
+			phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
+					 BIT(8));
 	}
 
 	val = phy_read(phydev, DP83867_CFG3);
-- 
2.17.1

On Thu, Oct 13, 2022 at 12:58:33PM +0530, Harini Katakam wrote:
> When RX strap in HW is not set to MODE 3 or 4, bit 7 and 8 in CF4
> register should be set. The former is already handled in
> dp83867_config_init; add the latter in SGMII specific initialization.
> 
> Signed-off-by: Harini Katakam <harini.katakam@amd.com>
> ---
>  drivers/net/phy/dp83867.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
> index 6939563d3b7c..a2aac9032af6 100644
> --- a/drivers/net/phy/dp83867.c
> +++ b/drivers/net/phy/dp83867.c
> @@ -853,6 +853,13 @@ static int dp83867_config_init(struct phy_device *phydev)
>  		else
>  			val &= ~DP83867_SGMII_TYPE;
>  		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
> +		/* This is a SW workaround for link instability if RX_CTRL is
> +		 * not strapped to mode 3 or 4 in HW. This is required for SGMII
> +		 * in addition to clearing bit 7, handled above.
> +		 */

Blank line before a comment please.

Should this have a fixes tag? Are there deployed boards which are
broken because of this? Or do you have a new board, using SGMII, which
is not deployed yet?

	 Andrew

Hi Andrew,

> -----Original Message-----
> From: Andrew Lunn <andrew@lunn.ch>
> Sent: Thursday, October 13, 2022 6:55 PM
> To: Katakam, Harini <harini.katakam@amd.com>
> Cc: hkallweit1@gmail.com; linux@armlinux.org.uk; davem@davemloft.net;
> edumazet@google.com; kuba@kernel.org; pabeni@redhat.com;
> netdev@vger.kernel.org; linux-kernel@vger.kernel.org;
> harinikatakamlinux@gmail.com; Simek, Michal <michal.simek@amd.com>;
> Pandey, Radhey Shyam <radhey.shyam.pandey@amd.com>
> Subject: Re: [PATCH] net: phy: dp83867: Extend RX strap quirk for SGMII
> mode
> 
> On Thu, Oct 13, 2022 at 12:58:33PM +0530, Harini Katakam wrote:
> > When RX strap in HW is not set to MODE 3 or 4, bit 7 and 8 in CF4
> > register should be set. The former is already handled in
> > dp83867_config_init; add the latter in SGMII specific initialization.
> >
> > Signed-off-by: Harini Katakam <harini.katakam@amd.com>
> > ---
> >  drivers/net/phy/dp83867.c | 7 +++++++
> >  1 file changed, 7 insertions(+)
> >
> > diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
> > index 6939563d3b7c..a2aac9032af6 100644
> > --- a/drivers/net/phy/dp83867.c
> > +++ b/drivers/net/phy/dp83867.c
> > @@ -853,6 +853,13 @@ static int dp83867_config_init(struct phy_device
> *phydev)
> >  		else
> >  			val &= ~DP83867_SGMII_TYPE;
> >  		phy_write_mmd(phydev, DP83867_DEVADDR,
> DP83867_SGMIICTL, val);
> > +		/* This is a SW workaround for link instability if RX_CTRL is
> > +		 * not strapped to mode 3 or 4 in HW. This is required for
> SGMII
> > +		 * in addition to clearing bit 7, handled above.
> > +		 */
> 
> Blank line before a comment please.
> 
> Should this have a fixes tag? Are there deployed boards which are broken
> because of this? Or do you have a new board, using SGMII, which is not
> deployed yet?

Thanks for the review. I will add a fixes tag on the original patch that added
SGMII support. I dint consider it first because this is workaround for a HW
strap issue. Yes, we have boards that are deployed.

Regards,
Harini