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[PATCH v2 1/6] x86/cpufeature: add cpu feature bit for LKGS

Xin Li posted 6 patches 3 years, 5 months ago
There is a newer version of this series
[PATCH v2 1/6] x86/cpufeature: add cpu feature bit for LKGS
Posted by Xin Li 3 years, 5 months ago 
From: "H. Peter Anvin (Intel)" <hpa@zytor.com>

Add the CPU feature bit for LKGS (Load "Kernel" GS).

LKGS instruction is introduced with Intel FRED (flexible return and
event delivery) specificaton
https://cdrdv2.intel.com/v1/dl/getContent/678938.

LKGS behaves like the MOV to GS instruction except that it loads
the base address into the IA32_KERNEL_GS_BASE MSR instead of the
GS segment’s descriptor cache, which is exactly what Linux kernel
does to load a user level GS base.  Thus, with LKGS, there is no
need to SWAPGS away from the kernel GS base.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Signed-off-by: Xin Li <xin3.li@intel.com>
---
 arch/x86/include/asm/cpufeatures.h       | 1 +
 tools/arch/x86/include/asm/cpufeatures.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index ef4775c6db01..459fb0c21dd4 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -308,6 +308,7 @@
 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
 #define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */
 #define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */
+#define X86_FEATURE_LKGS		(12*32+ 18) /* Load "kernel" (userspace) gs */
 
 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
 #define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */
diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
index ef4775c6db01..459fb0c21dd4 100644
--- a/tools/arch/x86/include/asm/cpufeatures.h
+++ b/tools/arch/x86/include/asm/cpufeatures.h
@@ -308,6 +308,7 @@
 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
 #define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */
 #define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */
+#define X86_FEATURE_LKGS		(12*32+ 18) /* Load "kernel" (userspace) gs */
 
 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
 #define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */
-- 
2.34.1
Re: [PATCH v2 1/6] x86/cpufeature: add cpu feature bit for LKGS
Posted by Chang S. Bae 3 years, 5 months ago 
On 10/10/2022 12:01 PM, Xin Li wrote:
> 
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index ef4775c6db01..459fb0c21dd4 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -308,6 +308,7 @@
>   /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
>   #define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */
>   #define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */
> +#define X86_FEATURE_LKGS		(12*32+ 18) /* Load "kernel" (userspace) gs */

The spec says [1]:
     "Execution of LKGS causes an invalid-opcode exception (#UD) if CPL >
      0."

Perhaps userspace has no interest in this. Then, we can add "" not to 
show "lkgs" in /proc/cpuinfo:
     +#define X86_FEATURE_LKGS		(12*32+ 18) /* "" Load "kernel" 
(userspace) gs */

Thanks,
Chang

[1] https://cdrdv2.intel.com/v1/dl/getContent/678938
RE: [PATCH v2 1/6] x86/cpufeature: add cpu feature bit for LKGS
Posted by Li, Xin3 3 years, 5 months ago 
> > diff --git a/arch/x86/include/asm/cpufeatures.h
> > b/arch/x86/include/asm/cpufeatures.h
> > index ef4775c6db01..459fb0c21dd4 100644
> > --- a/arch/x86/include/asm/cpufeatures.h
> > +++ b/arch/x86/include/asm/cpufeatures.h
> > @@ -308,6 +308,7 @@
> >   /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
> >   #define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI
> instructions */
> >   #define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512
> BFLOAT16 instructions */
> > +#define X86_FEATURE_LKGS		(12*32+ 18) /* Load "kernel"
> (userspace) gs */
> 
> The spec says [1]:
>      "Execution of LKGS causes an invalid-opcode exception (#UD) if CPL >
>       0."
> 
> Perhaps userspace has no interest in this. Then, we can add "" not to show
> "lkgs" in /proc/cpuinfo:
>      +#define X86_FEATURE_LKGS		(12*32+ 18) /* "" Load "kernel"
> (userspace) gs */

Good point!

> 
> Thanks,
> Chang
> 
> [1] https://cdrdv2.intel.com/v1/dl/getContent/678938
RE: [PATCH v2 1/6] x86/cpufeature: add cpu feature bit for LKGS
Posted by H. Peter Anvin 3 years, 5 months ago 
On October 13, 2022 12:35:23 PM PDT, "Li, Xin3" <xin3.li@intel.com> wrote:
>
>> > diff --git a/arch/x86/include/asm/cpufeatures.h
>> > b/arch/x86/include/asm/cpufeatures.h
>> > index ef4775c6db01..459fb0c21dd4 100644
>> > --- a/arch/x86/include/asm/cpufeatures.h
>> > +++ b/arch/x86/include/asm/cpufeatures.h
>> > @@ -308,6 +308,7 @@
>> >   /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
>> >   #define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI
>> instructions */
>> >   #define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512
>> BFLOAT16 instructions */
>> > +#define X86_FEATURE_LKGS		(12*32+ 18) /* Load "kernel"
>> (userspace) gs */
>> 
>> The spec says [1]:
>>      "Execution of LKGS causes an invalid-opcode exception (#UD) if CPL >
>>       0."
>> 
>> Perhaps userspace has no interest in this. Then, we can add "" not to show
>> "lkgs" in /proc/cpuinfo:
>>      +#define X86_FEATURE_LKGS		(12*32+ 18) /* "" Load "kernel"
>> (userspace) gs */
>
>Good point!
>
>> 
>> Thanks,
>> Chang
>> 
>> [1] https://cdrdv2.intel.com/v1/dl/getContent/678938
>

It would be useful for reviewers to mention that this is was a policy change on the maintainers' part. This is totally valid, of course, but making it explicit would perhaps help reduce potential confusion.

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