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[PATCH] net: mv643xx_eth: support MII/GMII/RGMII modes

David Yang posted 1 patch 1 year, 6 months ago
There is a newer version of this series
drivers/net/ethernet/marvell/mv643xx_eth.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
[PATCH] net: mv643xx_eth: support MII/GMII/RGMII modes
Posted by David Yang 1 year, 6 months ago 
On device reset all ports are automatically set to RGMII mode. MII
mode must be explicitly enabled.

If SoC has two Ethernet controllers, by setting both of them into MII
mode, the first controller enters GMII mode, while the second
controller is effectively disabled. This requires configuring (and
maybe enabling) the second controller in the device tree, even though
it cannot be used.

Signed-off-by: David Yang <mmyangfl@gmail.com>
---
 drivers/net/ethernet/marvell/mv643xx_eth.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
index b6be0552a..e2216ce5e 100644
--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
@@ -108,6 +108,7 @@ static char mv643xx_eth_driver_version[] = "1.4";
 #define TXQ_COMMAND			0x0048
 #define TXQ_FIX_PRIO_CONF		0x004c
 #define PORT_SERIAL_CONTROL1		0x004c
+#define  RGMII_EN			0x00000008
 #define  CLK125_BYPASS_EN		0x00000010
 #define TX_BW_RATE			0x0050
 #define TX_BW_MTU			0x0058
@@ -1245,6 +1246,21 @@ static void mv643xx_eth_adjust_link(struct net_device *dev)
 
 out_write:
 	wrlp(mp, PORT_SERIAL_CONTROL, pscr);
+
+	/* If two Ethernet controllers present in the SoC, MII modes follow the
+	 * following matrix:
+	 *
+	 * Port0 Mode	Port1 Mode	Port0 RGMII_EN	Port1 RGMII_EN
+	 * RGMII	RGMII		1		1
+	 * RGMII	MII/MMII	1		0
+	 * MII/MMII	RGMII		0		1
+	 * GMII		N/A		0		0
+	 *
+	 * To enable GMII on Port 0, Port 1 must also disable RGMII_EN too.
+	 */
+	if (!phy_interface_is_rgmii(dev->phydev))
+		wrlp(mp, PORT_SERIAL_CONTROL1,
+		     rdlp(mp, PORT_SERIAL_CONTROL1) & ~RGMII_EN);
 }
 
 /* statistics ***************************************************************/
-- 
2.35.1
Re: [PATCH] net: mv643xx_eth: support MII/GMII/RGMII modes
Posted by Andrew Lunn 1 year, 6 months ago 
On Sat, Oct 01, 2022 at 03:49:23AM +0800, David Yang wrote:
> On device reset all ports are automatically set to RGMII mode. MII
> mode must be explicitly enabled.
> 
> If SoC has two Ethernet controllers, by setting both of them into MII
> mode, the first controller enters GMII mode, while the second
> controller is effectively disabled. This requires configuring (and
> maybe enabling) the second controller in the device tree, even though
> it cannot be used.
> 
> Signed-off-by: David Yang <mmyangfl@gmail.com>
> ---
>  drivers/net/ethernet/marvell/mv643xx_eth.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
> index b6be0552a..e2216ce5e 100644
> --- a/drivers/net/ethernet/marvell/mv643xx_eth.c
> +++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
> @@ -108,6 +108,7 @@ static char mv643xx_eth_driver_version[] = "1.4";
>  #define TXQ_COMMAND			0x0048
>  #define TXQ_FIX_PRIO_CONF		0x004c
>  #define PORT_SERIAL_CONTROL1		0x004c
> +#define  RGMII_EN			0x00000008
>  #define  CLK125_BYPASS_EN		0x00000010
>  #define TX_BW_RATE			0x0050
>  #define TX_BW_MTU			0x0058
> @@ -1245,6 +1246,21 @@ static void mv643xx_eth_adjust_link(struct net_device *dev)
>  
>  out_write:
>  	wrlp(mp, PORT_SERIAL_CONTROL, pscr);
> +
> +	/* If two Ethernet controllers present in the SoC, MII modes follow the
> +	 * following matrix:
> +	 *
> +	 * Port0 Mode	Port1 Mode	Port0 RGMII_EN	Port1 RGMII_EN
> +	 * RGMII	RGMII		1		1
> +	 * RGMII	MII/MMII	1		0
> +	 * MII/MMII	RGMII		0		1
> +	 * GMII		N/A		0		0
> +	 *
> +	 * To enable GMII on Port 0, Port 1 must also disable RGMII_EN too.
> +	 */
> +	if (!phy_interface_is_rgmii(dev->phydev))
> +		wrlp(mp, PORT_SERIAL_CONTROL1,
> +		     rdlp(mp, PORT_SERIAL_CONTROL1) & ~RGMII_EN);

I could be reading this wrong, but doesn't this break the third line:

> +	 * MII/MMII	RGMII		0		1

Port 1 probes first, phy_interface is rgmii, so nothing happens, port1
RGMII_EN is left true.

Port 0 then probes, MII/MMII is not RGMII, so port1 RGMII_EN is
cleared, breaking port1.

I think you need to be more specific with the comparison.

  Andrew
Re: [PATCH] net: mv643xx_eth: support MII/GMII/RGMII modes
Posted by Yangfl 1 year, 6 months ago 
Andrew Lunn <andrew@lunn.ch> 于2022年10月1日周六 04:28写道：
>
> On Sat, Oct 01, 2022 at 03:49:23AM +0800, David Yang wrote:
> > On device reset all ports are automatically set to RGMII mode. MII
> > mode must be explicitly enabled.
> >
> > If SoC has two Ethernet controllers, by setting both of them into MII
> > mode, the first controller enters GMII mode, while the second
> > controller is effectively disabled. This requires configuring (and
> > maybe enabling) the second controller in the device tree, even though
> > it cannot be used.
> >
> > Signed-off-by: David Yang <mmyangfl@gmail.com>
> > ---
> >  drivers/net/ethernet/marvell/mv643xx_eth.c | 16 ++++++++++++++++
> >  1 file changed, 16 insertions(+)
> >
> > diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
> > index b6be0552a..e2216ce5e 100644
> > --- a/drivers/net/ethernet/marvell/mv643xx_eth.c
> > +++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
> > @@ -108,6 +108,7 @@ static char mv643xx_eth_driver_version[] = "1.4";
> >  #define TXQ_COMMAND                  0x0048
> >  #define TXQ_FIX_PRIO_CONF            0x004c
> >  #define PORT_SERIAL_CONTROL1         0x004c
> > +#define  RGMII_EN                    0x00000008
> >  #define  CLK125_BYPASS_EN            0x00000010
> >  #define TX_BW_RATE                   0x0050
> >  #define TX_BW_MTU                    0x0058
> > @@ -1245,6 +1246,21 @@ static void mv643xx_eth_adjust_link(struct net_device *dev)
> >
> >  out_write:
> >       wrlp(mp, PORT_SERIAL_CONTROL, pscr);
> > +
> > +     /* If two Ethernet controllers present in the SoC, MII modes follow the
> > +      * following matrix:
> > +      *
> > +      * Port0 Mode   Port1 Mode      Port0 RGMII_EN  Port1 RGMII_EN
> > +      * RGMII        RGMII           1               1
> > +      * RGMII        MII/MMII        1               0
> > +      * MII/MMII     RGMII           0               1
> > +      * GMII         N/A             0               0
> > +      *
> > +      * To enable GMII on Port 0, Port 1 must also disable RGMII_EN too.
> > +      */
> > +     if (!phy_interface_is_rgmii(dev->phydev))
> > +             wrlp(mp, PORT_SERIAL_CONTROL1,
> > +                  rdlp(mp, PORT_SERIAL_CONTROL1) & ~RGMII_EN);
>
> I could be reading this wrong, but doesn't this break the third line:
>
> > +      * MII/MMII     RGMII           0               1
>
> Port 1 probes first, phy_interface is rgmii, so nothing happens, port1
> RGMII_EN is left true.
>
> Port 0 then probes, MII/MMII is not RGMII, so port1 RGMII_EN is
> cleared, breaking port1.
>
> I think you need to be more specific with the comparison.
>
>   Andrew

Oh, I see. So you mean "phy-mode" property should belong to
controller, not port? I thought one controller can have at most one
port.
Re: [PATCH] net: mv643xx_eth: support MII/GMII/RGMII modes
Posted by Andrew Lunn 1 year, 6 months ago 
On Sat, Oct 01, 2022 at 04:47:42AM +0800, Yangfl wrote:
> Andrew Lunn <andrew@lunn.ch> 于2022年10月1日周六 04:28写道：
> >
> > On Sat, Oct 01, 2022 at 03:49:23AM +0800, David Yang wrote:
> > > On device reset all ports are automatically set to RGMII mode. MII
> > > mode must be explicitly enabled.
> > >
> > > If SoC has two Ethernet controllers, by setting both of them into MII
> > > mode, the first controller enters GMII mode, while the second
> > > controller is effectively disabled. This requires configuring (and
> > > maybe enabling) the second controller in the device tree, even though
> > > it cannot be used.
> > >
> > > Signed-off-by: David Yang <mmyangfl@gmail.com>
> > > ---
> > >  drivers/net/ethernet/marvell/mv643xx_eth.c | 16 ++++++++++++++++
> > >  1 file changed, 16 insertions(+)
> > >
> > > diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
> > > index b6be0552a..e2216ce5e 100644
> > > --- a/drivers/net/ethernet/marvell/mv643xx_eth.c
> > > +++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
> > > @@ -108,6 +108,7 @@ static char mv643xx_eth_driver_version[] = "1.4";
> > >  #define TXQ_COMMAND                  0x0048
> > >  #define TXQ_FIX_PRIO_CONF            0x004c
> > >  #define PORT_SERIAL_CONTROL1         0x004c
> > > +#define  RGMII_EN                    0x00000008
> > >  #define  CLK125_BYPASS_EN            0x00000010
> > >  #define TX_BW_RATE                   0x0050
> > >  #define TX_BW_MTU                    0x0058
> > > @@ -1245,6 +1246,21 @@ static void mv643xx_eth_adjust_link(struct net_device *dev)
> > >
> > >  out_write:
> > >       wrlp(mp, PORT_SERIAL_CONTROL, pscr);
> > > +
> > > +     /* If two Ethernet controllers present in the SoC, MII modes follow the
> > > +      * following matrix:
> > > +      *
> > > +      * Port0 Mode   Port1 Mode      Port0 RGMII_EN  Port1 RGMII_EN
> > > +      * RGMII        RGMII           1               1
> > > +      * RGMII        MII/MMII        1               0
> > > +      * MII/MMII     RGMII           0               1
> > > +      * GMII         N/A             0               0
> > > +      *
> > > +      * To enable GMII on Port 0, Port 1 must also disable RGMII_EN too.
> > > +      */
> > > +     if (!phy_interface_is_rgmii(dev->phydev))
> > > +             wrlp(mp, PORT_SERIAL_CONTROL1,
> > > +                  rdlp(mp, PORT_SERIAL_CONTROL1) & ~RGMII_EN);
> >
> > I could be reading this wrong, but doesn't this break the third line:
> >
> > > +      * MII/MMII     RGMII           0               1
> >
> > Port 1 probes first, phy_interface is rgmii, so nothing happens, port1
> > RGMII_EN is left true.
> >
> > Port 0 then probes, MII/MMII is not RGMII, so port1 RGMII_EN is
> > cleared, breaking port1.
> >
> > I think you need to be more specific with the comparison.
> >
> >   Andrew
> 
> Oh, I see. So you mean "phy-mode" property should belong to
> controller, not port? I thought one controller can have at most one
> port.

If you look at mv643xx_eth_shared_of_probe(), it appears a controller
can have multiple ports. And:

        if (dev_num == 3) {
                dev_err(&pdev->dev, "too many ports registered\n");
                return -EINVAL;
        }

I don't know the details?

	Andrew
[PATCH v3] net: mv643xx_eth: support MII/GMII/RGMII modes for Kirkwood
Posted by David Yang 1 year, 6 months ago 
Support mode switch properly, which is not available before.

If SoC has two Ethernet controllers, by setting both of them into MII
mode, the first controller enters GMII mode, while the second
controller is effectively disabled. This requires configuring (and
maybe enabling) the second controller in the device tree, even though
it cannot be used.

Signed-off-by: David Yang <mmyangfl@gmail.com>
---
v2: clarify modes work on controllers, read default value from PSC1
v3: Kirkwood only
 drivers/net/ethernet/marvell/mv643xx_eth.c | 48 ++++++++++++++++++++--
 1 file changed, 44 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
index b6be0552a..355bb8ba7 100644
--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
@@ -108,6 +108,7 @@ static char mv643xx_eth_driver_version[] = "1.4";
 #define TXQ_COMMAND			0x0048
 #define TXQ_FIX_PRIO_CONF		0x004c
 #define PORT_SERIAL_CONTROL1		0x004c
+#define  RGMII_EN			0x00000008
 #define  CLK125_BYPASS_EN		0x00000010
 #define TX_BW_RATE			0x0050
 #define TX_BW_MTU			0x0058
@@ -367,6 +368,7 @@ struct mv643xx_eth_private {
 	struct mv643xx_eth_shared_private *shared;
 	void __iomem *base;
 	int port_num;
+	bool kirkwood;
 
 	struct net_device *dev;
 
@@ -1215,6 +1217,7 @@ static void mv643xx_eth_adjust_link(struct net_device *dev)
 	             DISABLE_AUTO_NEG_SPEED_GMII |
 		     DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
 		     DISABLE_AUTO_NEG_FOR_DUPLEX;
+	u32 psc1r;
 
 	if (dev->phydev->autoneg == AUTONEG_ENABLE) {
 		/* enable auto negotiation */
@@ -1245,6 +1248,36 @@ static void mv643xx_eth_adjust_link(struct net_device *dev)
 
 out_write:
 	wrlp(mp, PORT_SERIAL_CONTROL, pscr);
+
+	if (mp->kirkwood) {
+		psc1r = rdlp(mp, PORT_SERIAL_CONTROL1);
+		/* On Kirkwood with two Ethernet controllers, if both of them
+		 * have RGMII_EN disabled, the first controller will be in GMII
+		 * mode and the second one is effectively disabled, instead of
+		 * two MII interfaces.
+		 *
+		 * To enable GMII in the first controller, the second one must
+		 * also be configured (and may be enabled) with RGMII_EN
+		 * disabled too, even though it cannot be used at all.
+		 */
+		switch (dev->phydev->interface) {
+		case PHY_INTERFACE_MODE_MII:
+		case PHY_INTERFACE_MODE_GMII:
+			psc1r &= ~RGMII_EN;
+			break;
+		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_ID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+			psc1r |= RGMII_EN;
+			break;
+		default:
+			/* Unknown; don't touch */
+			break;
+		}
+
+		wrlp(mp, PORT_SERIAL_CONTROL1, psc1r);
+	}
 }
 
 /* statistics ***************************************************************/
@@ -2975,11 +3008,16 @@ static int get_phy_mode(struct mv643xx_eth_private *mp)
 	if (dev->of_node)
 		err = of_get_phy_mode(dev->of_node, &iface);
 
-	/* Historical default if unspecified. We could also read/write
-	 * the interface state in the PSC1
+	/* Read the interface state in the PSC1.
+	 *
+	 * Modes of two devices may interact on Kirkwood. Currently there is no
+	 * way to detect another device within this scope; blindly set MII
+	 * here.
 	 */
 	if (!dev->of_node || err)
-		iface = PHY_INTERFACE_MODE_GMII;
+		iface = rdlp(mp, PORT_SERIAL_CONTROL1) & RGMII_EN ?
+			PHY_INTERFACE_MODE_RGMII : mp->kirkwood ?
+			PHY_INTERFACE_MODE_MII : PHY_INTERFACE_MODE_GMII;
 	return iface;
 }
 
@@ -3124,9 +3162,11 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
 	 * all other SoCs/System Controllers using this driver.
 	 */
 	if (of_device_is_compatible(pdev->dev.of_node,
-				    "marvell,kirkwood-eth-port"))
+				    "marvell,kirkwood-eth-port")) {
 		wrlp(mp, PORT_SERIAL_CONTROL1,
 		     rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN);
+		mp->kirkwood = 1;
+	}
 
 	/*
 	 * Start with a default rate, and if there is a clock, allow
-- 
2.35.1
[PATCH v4] net: mv643xx_eth: support MII/GMII/RGMII modes for Kirkwood
Posted by David Yang 1 year, 6 months ago 
Support mode switch properly, which is not available before.

If SoC has two Ethernet controllers, by setting both of them into MII
mode, the first controller enters GMII mode, while the second
controller is effectively disabled. This requires configuring (and
maybe enabling) the second controller in the device tree, even though
it cannot be used.

Signed-off-by: David Yang <mmyangfl@gmail.com>
---
v2: clarify modes work on controllers, read default value from PSC1
v3: Kirkwood only
v4: cleanup
 drivers/net/ethernet/marvell/mv643xx_eth.c | 57 +++++++++++++++++++---
 1 file changed, 51 insertions(+), 6 deletions(-)

diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
index b6be0552a..4d4ee36b5 100644
--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
@@ -108,6 +108,7 @@ static char mv643xx_eth_driver_version[] = "1.4";
 #define TXQ_COMMAND			0x0048
 #define TXQ_FIX_PRIO_CONF		0x004c
 #define PORT_SERIAL_CONTROL1		0x004c
+#define  RGMII_EN			0x00000008
 #define  CLK125_BYPASS_EN		0x00000010
 #define TX_BW_RATE			0x0050
 #define TX_BW_MTU			0x0058
@@ -1215,6 +1216,7 @@ static void mv643xx_eth_adjust_link(struct net_device *dev)
 	             DISABLE_AUTO_NEG_SPEED_GMII |
 		     DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
 		     DISABLE_AUTO_NEG_FOR_DUPLEX;
+	u32 psc1r;
 
 	if (dev->phydev->autoneg == AUTONEG_ENABLE) {
 		/* enable auto negotiation */
@@ -1245,6 +1247,38 @@ static void mv643xx_eth_adjust_link(struct net_device *dev)
 
 out_write:
 	wrlp(mp, PORT_SERIAL_CONTROL, pscr);
+
+	if (dev->dev->of_node &&
+	    of_device_is_compatible(dev->dev->of_node,
+				    "marvell,kirkwood-eth-port")) {
+		psc1r = rdlp(mp, PORT_SERIAL_CONTROL1);
+		/* On Kirkwood with two Ethernet controllers, if both of them
+		 * have RGMII_EN disabled, the first controller will be in GMII
+		 * mode and the second one is effectively disabled, instead of
+		 * two MII interfaces.
+		 *
+		 * To enable GMII in the first controller, the second one must
+		 * also be configured (and may be enabled) with RGMII_EN
+		 * disabled too, even though it cannot be used at all.
+		 */
+		switch (dev->phydev->interface) {
+		case PHY_INTERFACE_MODE_MII:
+		case PHY_INTERFACE_MODE_GMII:
+			psc1r &= ~RGMII_EN;
+			break;
+		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_ID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+			psc1r |= RGMII_EN;
+			break;
+		default:
+			/* Unknown; don't touch */
+			break;
+		}
+
+		wrlp(mp, PORT_SERIAL_CONTROL1, psc1r);
+	}
 }
 
 /* statistics ***************************************************************/
@@ -2972,15 +3006,26 @@ static int get_phy_mode(struct mv643xx_eth_private *mp)
 	phy_interface_t iface;
 	int err;
 
-	if (dev->of_node)
+	if (dev->of_node) {
 		err = of_get_phy_mode(dev->of_node, &iface);
+		if (!err)
+			return iface;
+	}
+
+	/* Read the interface state in the PSC1 */
+	if (rdlp(mp, PORT_SERIAL_CONTROL1) & RGMII_EN)
+		return PHY_INTERFACE_MODE_RGMII;
 
-	/* Historical default if unspecified. We could also read/write
-	 * the interface state in the PSC1
+	/* Modes of two devices may interact on Kirkwood. Currently there is no
+	 * way to detect another device within this scope; blindly set MII
+	 * here.
 	 */
-	if (!dev->of_node || err)
-		iface = PHY_INTERFACE_MODE_GMII;
-	return iface;
+	if (dev->of_node &&
+	    of_device_is_compatible(dev->of_node, "marvell,kirkwood-eth"))
+		return PHY_INTERFACE_MODE_MII;
+
+	/* Historical default if unspecified */
+	return PHY_INTERFACE_MODE_GMII;
 }
 
 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
-- 
2.35.1
[PATCH v2] net: mv643xx_eth: support MII/GMII/RGMII modes
Posted by David Yang 1 year, 6 months ago 
Support mode switch properly, which is not available before.

If SoC has two Ethernet controllers, by setting both of them into MII
mode, the first controller enters GMII mode, while the second
controller is effectively disabled. This requires configuring (and
maybe enabling) the second controller in the device tree, even though
it cannot be used.

Signed-off-by: David Yang <mmyangfl@gmail.com>
---
v2: clarify modes work on controllers, read default value from PSC1
 drivers/net/ethernet/marvell/mv643xx_eth.c | 36 ++++++++++++++++++++--
 1 file changed, 33 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
index b6be0552a..ddaccc979 100644
--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
@@ -108,6 +108,7 @@ static char mv643xx_eth_driver_version[] = "1.4";
 #define TXQ_COMMAND			0x0048
 #define TXQ_FIX_PRIO_CONF		0x004c
 #define PORT_SERIAL_CONTROL1		0x004c
+#define  RGMII_EN			0x00000008
 #define  CLK125_BYPASS_EN		0x00000010
 #define TX_BW_RATE			0x0050
 #define TX_BW_MTU			0x0058
@@ -1215,6 +1216,7 @@ static void mv643xx_eth_adjust_link(struct net_device *dev)
 	             DISABLE_AUTO_NEG_SPEED_GMII |
 		     DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
 		     DISABLE_AUTO_NEG_FOR_DUPLEX;
+	u32 psc1r = rdlp(mp, PORT_SERIAL_CONTROL1);
 
 	if (dev->phydev->autoneg == AUTONEG_ENABLE) {
 		/* enable auto negotiation */
@@ -1245,6 +1247,30 @@ static void mv643xx_eth_adjust_link(struct net_device *dev)
 
 out_write:
 	wrlp(mp, PORT_SERIAL_CONTROL, pscr);
+
+	/* If two Ethernet controllers present in the SoC, and both of them have
+	 * RGMII_EN disabled, the first controller will be in GMII mode and the
+	 * second one is effectively disabled, instead of two MII interfaces.
+	 *
+	 * To enable GMII in the first controller, the second one must also be
+	 * configured (and may be enabled) with RGMII_EN disabled too, even
+	 * though it cannot be used at all.
+	 */
+	switch (dev->phydev->interface) {
+	case PHY_INTERFACE_MODE_MII:
+	case PHY_INTERFACE_MODE_GMII:
+		wrlp(mp, PORT_SERIAL_CONTROL1, psc1r & ~RGMII_EN);
+		break;
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_ID:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+		wrlp(mp, PORT_SERIAL_CONTROL1, psc1r | RGMII_EN);
+		break;
+	default:
+		/* Unknown; don't touch */
+		break;
+	}
 }
 
 /* statistics ***************************************************************/
@@ -2975,11 +3001,15 @@ static int get_phy_mode(struct mv643xx_eth_private *mp)
 	if (dev->of_node)
 		err = of_get_phy_mode(dev->of_node, &iface);
 
-	/* Historical default if unspecified. We could also read/write
-	 * the interface state in the PSC1
+	/* Read the interface state in the PSC1.
+	 *
+	 * Modes of two devices may interact; see comments in
+	 * mv643xx_eth_adjust_link. Currently there is no way to detect another
+	 * device within this scope; blindly set MII here.
 	 */
 	if (!dev->of_node || err)
-		iface = PHY_INTERFACE_MODE_GMII;
+		iface = rdlp(mp, PORT_SERIAL_CONTROL1) & RGMII_EN ?
+			PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_MII;
 	return iface;
 }
 
-- 
2.35.1
Re: [PATCH v2] net: mv643xx_eth: support MII/GMII/RGMII modes
Posted by Paolo Abeni 1 year, 6 months ago 
Hello,

On Sat, 2022-10-01 at 04:39 +0800, David Yang wrote:
> Support mode switch properly, which is not available before.
> 
> If SoC has two Ethernet controllers, by setting both of them into MII
> mode, the first controller enters GMII mode, while the second
> controller is effectively disabled. This requires configuring (and
> maybe enabling) the second controller in the device tree, even though
> it cannot be used.
> 
> Signed-off-by: David Yang <mmyangfl@gmail.com>

It looks like that despite the subj change, this is superseded by:

https://patchwork.kernel.org/project/netdevbpf/patch/20221001174524.2007912-1-mmyangfl@gmail.com/

I'm updating the PW accordingly. Please let me know if you intended
otherwise.

Thanks,

Paolo

Patchew 2.1-devel-0870f84

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