.../devicetree/bindings/net/marvell,pp2.yaml | 292 ++++++++++++++++++ .../devicetree/bindings/net/marvell-pp2.txt | 141 --------- MAINTAINERS | 2 +- 3 files changed, 293 insertions(+), 142 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/marvell,pp2.yaml delete mode 100644 Documentation/devicetree/bindings/net/marvell-pp2.txt
This converts the marvell,pp2 bindings from text to proper schema.
Move 'marvell,system-controller' and 'dma-coherent' properties from
port up to the controller node, to match what is actually done in DT.
Signed-off-by: Michał Grzelak <mig@semihalf.com>
---
.../devicetree/bindings/net/marvell,pp2.yaml | 292 ++++++++++++++++++
.../devicetree/bindings/net/marvell-pp2.txt | 141 ---------
MAINTAINERS | 2 +-
3 files changed, 293 insertions(+), 142 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/marvell,pp2.yaml
delete mode 100644 Documentation/devicetree/bindings/net/marvell-pp2.txt
diff --git a/Documentation/devicetree/bindings/net/marvell,pp2.yaml b/Documentation/devicetree/bindings/net/marvell,pp2.yaml
new file mode 100644
index 000000000000..b4589594a0cc
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/marvell,pp2.yaml
@@ -0,0 +1,292 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/marvell,pp2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell CN913X / Marvell Armada 375, 7K, 8K Ethernet Controller
+
+maintainers:
+ - Marcin Wojtas <mw@semihalf.com>
+ - Russell King <linux@armlinux.org>
+
+description: |
+ Marvell Armada 375 Ethernet Controller (PPv2.1)
+ Marvell Armada 7K/8K Ethernet Controller (PPv2.2)
+ Marvell CN913X Ethernet Controller (PPv2.3)
+
+patternProperties:
+
+ '^interrupt': true
+ '^#.*-cells$': true
+
+ '^eth[0-9a-f]*(@.*)?$':
+ type: object
+ properties:
+
+ interrupts:
+ minItems: 1
+ maxItems: 10
+ description: interrupt(s) for the port
+
+ interrupt-names:
+ minItems: 1
+ maxItems: 10
+
+ items:
+ oneOf:
+ - pattern: "^hif[0-8]$"
+ - pattern: "^tx-cpu[0-3]$"
+ deprecated: true
+ - const: link
+ - const: rx-shared
+ deprecated: true
+
+ description: >
+ if more than a single interrupt for is given, must be the
+ name associated to the interrupts listed. Valid names are:
+ "hifX", with X in [0..8], and "link". The names "tx-cpu0",
+ "tx-cpu1", "tx-cpu2", "tx-cpu3" and "rx-shared" are supported
+ for backward compatibility but shouldn't be used for new
+ additions.
+
+ port-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: ID of the port from the MAC point of view.
+
+ phy-mode:
+ $ref: "ethernet-controller.yaml#/properties/phy-mode"
+
+ marvell,loopback:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: port is loopback mode.
+
+ phy:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: >
+ a phandle to a phy node defining the PHY address
+ (as the reg property, a single integer).
+
+ required:
+ - interrupts
+ - port-id
+ - phy-mode
+
+properties:
+
+ dma-coherent: true
+
+ compatible:
+ enum:
+ - marvell,armada-375-pp2
+ - marvell,armada-7k-pp2
+
+ reg:
+ minItems: 3
+ maxItems: 4
+
+ marvell,system-controller:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: a phandle to the system controller.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+allOf:
+
+ - $ref: ethernet-controller.yaml#
+
+ - if:
+ not:
+ patternProperties:
+ '^eth[0-9a-f]*(@.*)?$':
+ properties:
+ interrupts:
+ maxItems: 1
+
+ then:
+ patternProperties:
+ '^eth[0-9a-f]*(@.*)?$':
+ required:
+ - interrupt-names
+
+ - if:
+ properties:
+ compatible:
+ const: marvell,armada-375-pp2
+
+ then:
+ properties:
+
+ clocks:
+ items:
+ - description: main controller clock
+ - description: GOP clock
+
+ clock-names:
+ minItems: 2
+ maxItems: 2
+ items:
+ enum:
+ - pp_clk
+ - gop_clk
+
+ reg:
+ description: |
+ For "marvell,armada-375-pp2", must contain the following register sets:
+ - common controller registers
+ - LMS registers
+ - one register area per Ethernet port
+
+ else:
+
+ patternProperties:
+ '^eth[0-9a-f]*(@.*)?$':
+ properties:
+ gop-port-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: >
+ only for marvell,armada-7k-pp2, ID of the port from the
+ GOP (Group Of Ports) point of view. This ID is used to index the
+ per-port registers in the second register area.
+
+ required:
+ - gop-port-id
+
+ properties:
+
+ clocks:
+ items:
+ - description: main controller clock
+ - description: GOP clock
+ - description: MG clock
+ - description: MG Core clock
+ - description: AXI clock
+
+ clock-names:
+ minItems: 5
+ maxItems: 5
+ items:
+ enum:
+ - gop_clk
+ - pp_clk
+ - mg_clk
+ - mg_core_clk
+ - axi_clk
+
+ reg:
+ description: |
+ For "marvell,armada-7k-pp2" used by 7K/8K and CN913X, must contain the following register sets:
+ - packet processor registers
+ - networking interfaces registers
+ - CM3 address space used for TX Flow Control
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ // For Armada 375 variant
+ #include <dt-bindings/interrupt-controller/mvebu-icu.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ ethernet@f0000 {
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ compatible = "marvell,armada-375-pp2";
+ reg = <0xf0000 0xa000>,
+ <0xc0000 0x3060>,
+ <0xc4000 0x100>,
+ <0xc5000 0x100>;
+ clocks = <&gateclk 3>, <&gateclk 19>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "pp_clk", "gop_clk";
+
+ eth0: eth0@c4000 {
+ reg = <0xc4000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ port-id = <0>;
+ phy = <&phy0>;
+ phy-mode = "gmii";
+ };
+
+ eth1: eth1@c5000 {
+ reg = <0xc5000>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ port-id = <1>;
+ phy = <&phy3>;
+ phy-mode = "gmii";
+ };
+ };
+
+ - |
+ // For Armada 7k/8k and Cn913x variants
+ #include <dt-bindings/interrupt-controller/mvebu-icu.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ cpm_ethernet: ethernet@0 {
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ compatible = "marvell,armada-7k-pp2";
+ reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>;
+ clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>,
+ <&cpm_syscon0 1 5>, <&cpm_syscon0 1 6>, <&cpm_syscon0 1 18>;
+ clock-names = "pp_clk", "gop_clk", "mg_clk", "mg_core_clk", "axi_clk";
+
+ eth00: eth0 {
+ interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 59 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 63 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 67 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 71 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hif0", "hif1", "hif2", "hif3", "hif4",
+ "hif5", "hif6", "hif7", "hif8", "link";
+ phy-mode = "10gbase-r";
+ port-id = <0>;
+ gop-port-id = <0>;
+ };
+
+ eth01: eth1 {
+ interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 60 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 64 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 68 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 72 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hif0", "hif1", "hif2", "hif3", "hif4",
+ "hif5", "hif6", "hif7", "hif8", "link";
+ phy-mode = "rgmii-id";
+ port-id = <1>;
+ gop-port-id = <2>;
+ };
+
+ eth02: eth2 {
+ interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 61 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 65 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 69 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 73 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hif0", "hif1", "hif2", "hif3", "hif4",
+ "hif5", "hif6", "hif7", "hif8", "link";
+ phy-mode = "gmii";
+ port-id = <2>;
+ gop-port-id = <3>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/net/marvell-pp2.txt b/Documentation/devicetree/bindings/net/marvell-pp2.txt
deleted file mode 100644
index ce15c173f43f..000000000000
--- a/Documentation/devicetree/bindings/net/marvell-pp2.txt
+++ /dev/null
@@ -1,141 +0,0 @@
-* Marvell Armada 375 Ethernet Controller (PPv2.1)
- Marvell Armada 7K/8K Ethernet Controller (PPv2.2)
- Marvell CN913X Ethernet Controller (PPv2.3)
-
-Required properties:
-
-- compatible: should be one of:
- "marvell,armada-375-pp2"
- "marvell,armada-7k-pp2"
-- reg: addresses and length of the register sets for the device.
- For "marvell,armada-375-pp2", must contain the following register
- sets:
- - common controller registers
- - LMS registers
- - one register area per Ethernet port
- For "marvell,armada-7k-pp2" used by 7K/8K and CN913X, must contain the following register
- sets:
- - packet processor registers
- - networking interfaces registers
- - CM3 address space used for TX Flow Control
-
-- clocks: pointers to the reference clocks for this device, consequently:
- - main controller clock (for both armada-375-pp2 and armada-7k-pp2)
- - GOP clock (for both armada-375-pp2 and armada-7k-pp2)
- - MG clock (only for armada-7k-pp2)
- - MG Core clock (only for armada-7k-pp2)
- - AXI clock (only for armada-7k-pp2)
-- clock-names: names of used clocks, must be "pp_clk", "gop_clk", "mg_clk",
- "mg_core_clk" and "axi_clk" (the 3 latter only for armada-7k-pp2).
-
-The ethernet ports are represented by subnodes. At least one port is
-required.
-
-Required properties (port):
-
-- interrupts: interrupt(s) for the port
-- port-id: ID of the port from the MAC point of view
-- gop-port-id: only for marvell,armada-7k-pp2, ID of the port from the
- GOP (Group Of Ports) point of view. This ID is used to index the
- per-port registers in the second register area.
-- phy-mode: See ethernet.txt file in the same directory
-
-Optional properties (port):
-
-- marvell,loopback: port is loopback mode
-- phy: a phandle to a phy node defining the PHY address (as the reg
- property, a single integer).
-- interrupt-names: if more than a single interrupt for is given, must be the
- name associated to the interrupts listed. Valid names are:
- "hifX", with X in [0..8], and "link". The names "tx-cpu0",
- "tx-cpu1", "tx-cpu2", "tx-cpu3" and "rx-shared" are supported
- for backward compatibility but shouldn't be used for new
- additions.
-- marvell,system-controller: a phandle to the system controller.
-
-Example for marvell,armada-375-pp2:
-
-ethernet@f0000 {
- compatible = "marvell,armada-375-pp2";
- reg = <0xf0000 0xa000>,
- <0xc0000 0x3060>,
- <0xc4000 0x100>,
- <0xc5000 0x100>;
- clocks = <&gateclk 3>, <&gateclk 19>;
- clock-names = "pp_clk", "gop_clk";
-
- eth0: eth0@c4000 {
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- port-id = <0>;
- phy = <&phy0>;
- phy-mode = "gmii";
- };
-
- eth1: eth1@c5000 {
- interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
- port-id = <1>;
- phy = <&phy3>;
- phy-mode = "gmii";
- };
-};
-
-Example for marvell,armada-7k-pp2:
-
-cpm_ethernet: ethernet@0 {
- compatible = "marvell,armada-7k-pp22";
- reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>;
- clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>,
- <&cpm_syscon0 1 5>, <&cpm_syscon0 1 6>, <&cpm_syscon0 1 18>;
- clock-names = "pp_clk", "gop_clk", "mg_clk", "mg_core_clk", "axi_clk";
-
- eth0: eth0 {
- interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 59 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 63 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 67 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 71 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hif0", "hif1", "hif2", "hif3", "hif4",
- "hif5", "hif6", "hif7", "hif8", "link";
- port-id = <0>;
- gop-port-id = <0>;
- };
-
- eth1: eth1 {
- interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 60 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 64 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 68 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 72 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hif0", "hif1", "hif2", "hif3", "hif4",
- "hif5", "hif6", "hif7", "hif8", "link";
- port-id = <1>;
- gop-port-id = <2>;
- };
-
- eth2: eth2 {
- interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 61 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 65 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 69 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 73 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hif0", "hif1", "hif2", "hif3", "hif4",
- "hif5", "hif6", "hif7", "hif8", "link";
- port-id = <2>;
- gop-port-id = <3>;
- };
-};
diff --git a/MAINTAINERS b/MAINTAINERS
index 9ae989b32ebb..3d8e64bf7ae6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12191,7 +12191,7 @@ M: Marcin Wojtas <mw@semihalf.com>
M: Russell King <linux@armlinux.org.uk>
L: netdev@vger.kernel.org
S: Maintained
-F: Documentation/devicetree/bindings/net/marvell-pp2.txt
+F: Documentation/devicetree/bindings/net/marvell,pp2.yaml
F: drivers/net/ethernet/marvell/mvpp2/
MARVELL MWIFIEX WIRELESS DRIVER
--
7FED8E4C2F58949CA919EEE5AAFD24434A5ECFEF
Hi,
Thank you for the patch.
> +
> +properties:
> +
> + dma-coherent: true
> +
> + compatible:
> + enum:
> + - marvell,armada-375-pp2
> + - marvell,armada-7k-pp2
I double checked with armada-cp11x.dtsi and the driver. Please
s/marvell,armada-7k-pp2/marvell,armada-7k-pp22/ in all occurrences.
> +
> + reg:
> + minItems: 3
> + maxItems: 4
> +
> +examples:
> + - |
> + // For Armada 375 variant
> + #include <dt-bindings/interrupt-controller/mvebu-icu.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + ethernet@f0000 {
> + interrupt-controller;
> + #interrupt-cells = <3>;
interrupt-controller and #interrupt-cells are not valid properties for
this controller.
> + compatible = "marvell,armada-375-pp2";
> + reg = <0xf0000 0xa000>,
> + <0xc0000 0x3060>,
> + <0xc4000 0x100>,
> + <0xc5000 0x100>;
> + clocks = <&gateclk 3>, <&gateclk 19>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clock-names = "pp_clk", "gop_clk";
> +
> + eth0: eth0@c4000 {
> + reg = <0xc4000>;
> + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> + port-id = <0>;
> + phy = <&phy0>;
> + phy-mode = "gmii";
> + };
> +
> + eth1: eth1@c5000 {
> + reg = <0xc5000>;
> + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> + port-id = <1>;
> + phy = <&phy3>;
> + phy-mode = "gmii";
> + };
> + };
> +
> + - |
> + // For Armada 7k/8k and Cn913x variants
> + #include <dt-bindings/interrupt-controller/mvebu-icu.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + cpm_ethernet: ethernet@0 {
> + interrupt-controller;
> + #interrupt-cells = <3>;
interrupt-controller and #interrupt-cells are not valid properties for
this controller.
Best regards,
Marcin
On 22/09/2022 23:10, Michał Grzelak wrote: > This converts the marvell,pp2 bindings from text to proper schema. > > Move 'marvell,system-controller' and 'dma-coherent' properties from > port up to the controller node, to match what is actually done in DT. > > Signed-off-by: Michał Grzelak <mig@semihalf.com> > --- > .../devicetree/bindings/net/marvell,pp2.yaml | 292 ++++++++++++++++++ > .../devicetree/bindings/net/marvell-pp2.txt | 141 --------- > MAINTAINERS | 2 +- > 3 files changed, 293 insertions(+), 142 deletions(-) > create mode 100644 Documentation/devicetree/bindings/net/marvell,pp2.yaml > delete mode 100644 Documentation/devicetree/bindings/net/marvell-pp2.txt > > diff --git a/Documentation/devicetree/bindings/net/marvell,pp2.yaml b/Documentation/devicetree/bindings/net/marvell,pp2.yaml > new file mode 100644 > index 000000000000..b4589594a0cc > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/marvell,pp2.yaml > @@ -0,0 +1,292 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/net/marvell,pp2.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Marvell CN913X / Marvell Armada 375, 7K, 8K Ethernet Controller > + > +maintainers: > + - Marcin Wojtas <mw@semihalf.com> > + - Russell King <linux@armlinux.org> > + > +description: | > + Marvell Armada 375 Ethernet Controller (PPv2.1) > + Marvell Armada 7K/8K Ethernet Controller (PPv2.2) > + Marvell CN913X Ethernet Controller (PPv2.3) > + properties go first. > +patternProperties: > + no need for blank line. > + '^interrupt': true This is not a pattern.. > + '^#.*-cells$': true ??? Nope. Please start from scratch either from recent similar bindings or from example-schema. > + > + '^eth[0-9a-f]*(@.*)?$': > + type: object > + properties: > + > + interrupts: > + minItems: 1 > + maxItems: 10 > + description: interrupt(s) for the port > + > + interrupt-names: > + minItems: 1 > + maxItems: 10 > + > + items: > + oneOf: > + - pattern: "^hif[0-8]$" > + - pattern: "^tx-cpu[0-3]$" > + deprecated: true > + - const: link > + - const: rx-shared > + deprecated: true List hast to be specific. > + > + description: > > + if more than a single interrupt for is given, must be the > + name associated to the interrupts listed. Valid names are: > + "hifX", with X in [0..8], and "link". The names "tx-cpu0", > + "tx-cpu1", "tx-cpu2", "tx-cpu3" and "rx-shared" are supported > + for backward compatibility but shouldn't be used for new > + additions. > + > + port-id: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: ID of the port from the MAC point of view. > + > + phy-mode: > + $ref: "ethernet-controller.yaml#/properties/phy-mode" > + > + marvell,loopback: > + $ref: /schemas/types.yaml#/definitions/flag > + description: port is loopback mode. > + > + phy: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > > + a phandle to a phy node defining the PHY address > + (as the reg property, a single integer). > + > + required: > + - interrupts > + - port-id > + - phy-mode > + > +properties: > + > + dma-coherent: true > + > + compatible: This goes first. > + enum: > + - marvell,armada-375-pp2 > + - marvell,armada-7k-pp2 > + > + reg: > + minItems: 3 > + maxItems: 4 > + > + marvell,system-controller: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: a phandle to the system controller. > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + > +allOf: > + No need for blank line. > + - $ref: ethernet-controller.yaml# > + > + - if: > + not: > + patternProperties: > + '^eth[0-9a-f]*(@.*)?$': > + properties: > + interrupts: > + maxItems: 1 > + > + then: > + patternProperties: > + '^eth[0-9a-f]*(@.*)?$': > + required: > + - interrupt-names Skip this. > + > + - if: > + properties: > + compatible: > + const: marvell,armada-375-pp2 > + > + then: > + properties: > + Skip the blank lines after each new block. > + clocks: > + items: > + - description: main controller clock > + - description: GOP clock > + > + clock-names: > + minItems: 2 > + maxItems: 2 > + items: > + enum: > + - pp_clk > + - gop_clk > + > + reg: > + description: | > + For "marvell,armada-375-pp2", must contain the following register sets: > + - common controller registers > + - LMS registers > + - one register area per Ethernet port > + > + else: > + > + patternProperties: > + '^eth[0-9a-f]*(@.*)?$': > + properties: > + gop-port-id: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: > > + only for marvell,armada-7k-pp2, ID of the port from the > + GOP (Group Of Ports) point of view. This ID is used to index the > + per-port registers in the second register area. > + > + required: > + - gop-port-id > + > + properties: > + > + clocks: > + items: > + - description: main controller clock > + - description: GOP clock > + - description: MG clock > + - description: MG Core clock > + - description: AXI clock Why clocks appear only here? All devices require clocks, so this should be in top level. > + > + clock-names: > + minItems: 5 > + maxItems: 5 > + items: > + enum: > + - gop_clk > + - pp_clk > + - mg_clk > + - mg_core_clk > + - axi_clk > + > + reg: > + description: | > + For "marvell,armada-7k-pp2" used by 7K/8K and CN913X, must contain the following register sets: > + - packet processor registers > + - networking interfaces registers > + - CM3 address space used for TX Flow Control Do not define properties in allOf:if:then, but in top-level place. Really, start with example-schema. This deviates too much from existing coding style. Best regards, Krzysztof
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