Add support for SGMII mode in both fixed-link MAC2MAC master mode and
MAC2PHY modes for CPSW5G ports.
Add SGMII mode to the list of extra_modes in j7200_cpswxg_pdata.
The MAC2PHY mode has been tested in fixed-link mode using a bootstrapped
PHY. The MAC2MAC mode has been tested by a customer with J7200 SoC on
their device.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
drivers/net/ethernet/ti/am65-cpsw-nuss.c | 19 ++++++++++++++++---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
index 1739c389af20..3f40178436ff 100644
--- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
@@ -75,7 +75,15 @@
#define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 0x31C
#define AM65_CPSW_SGMII_CONTROL_REG 0x010
+#define AM65_CPSW_SGMII_MR_ADV_ABILITY_REG 0x018
#define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE BIT(0)
+#define AM65_CPSW_SGMII_CONTROL_MASTER_MODE BIT(5)
+
+#define MAC2MAC_MR_ADV_ABILITY_BASE (BIT(15) | BIT(0))
+#define MAC2MAC_MR_ADV_ABILITY_FULLDUPLEX BIT(12)
+#define MAC2MAC_MR_ADV_ABILITY_1G BIT(11)
+#define MAC2MAC_MR_ADV_ABILITY_100M BIT(10)
+#define MAC2PHY_MR_ADV_ABILITY BIT(0)
#define AM65_CPSW_CTL_VLAN_AWARE BIT(1)
#define AM65_CPSW_CTL_P0_ENABLE BIT(2)
@@ -1493,6 +1501,7 @@ static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned in
struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data,
phylink_config);
struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave);
+ u32 mr_adv_ability = MAC2MAC_MR_ADV_ABILITY_BASE;
struct am65_cpsw_common *common = port->common;
struct fwnode_handle *fwnode;
bool fixed_link = false;
@@ -2105,8 +2114,12 @@ am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx)
__set_bit(PHY_INTERFACE_MODE_RMII,
port->slave.phylink_config.supported_interfaces);
} else if (common->pdata.extra_modes & BIT(port->slave.phy_if)) {
- __set_bit(PHY_INTERFACE_MODE_QSGMII,
- port->slave.phylink_config.supported_interfaces);
+ if (port->slave.phy_if == PHY_INTERFACE_MODE_QSGMII)
+ __set_bit(PHY_INTERFACE_MODE_QSGMII,
+ port->slave.phylink_config.supported_interfaces);
+ else
+ __set_bit(PHY_INTERFACE_MODE_SGMII,
+ port->slave.phylink_config.supported_interfaces);
} else {
dev_err(dev, "selected phy-mode is not supported\n");
return -EOPNOTSUPP;
@@ -2744,7 +2757,7 @@ static const struct am65_cpsw_pdata j7200_cpswxg_pdata = {
.quirks = 0,
.ale_dev_id = "am64-cpswxg",
.fdqring_mode = K3_RINGACC_RING_MODE_RING,
- .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII),
+ .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII),
};
static const struct of_device_id am65_cpsw_nuss_of_mtable[] = {
--
2.25.1On Wed, Sep 14, 2022 at 03:20:51PM +0530, Siddharth Vadapalli wrote:
> Add support for SGMII mode in both fixed-link MAC2MAC master mode and
> MAC2PHY modes for CPSW5G ports.
>
> Add SGMII mode to the list of extra_modes in j7200_cpswxg_pdata.
>
> The MAC2PHY mode has been tested in fixed-link mode using a bootstrapped
> PHY. The MAC2MAC mode has been tested by a customer with J7200 SoC on
> their device.
>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
> drivers/net/ethernet/ti/am65-cpsw-nuss.c | 19 ++++++++++++++++---
> 1 file changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
> index 1739c389af20..3f40178436ff 100644
> --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c
> +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
> @@ -75,7 +75,15 @@
> #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 0x31C
>
> #define AM65_CPSW_SGMII_CONTROL_REG 0x010
> +#define AM65_CPSW_SGMII_MR_ADV_ABILITY_REG 0x018
This doesn't seem to be used in this patch, should it be part of some
other patch in the series?
> #define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE BIT(0)
> +#define AM65_CPSW_SGMII_CONTROL_MASTER_MODE BIT(5)
Ditto.
> +
> +#define MAC2MAC_MR_ADV_ABILITY_BASE (BIT(15) | BIT(0))
> +#define MAC2MAC_MR_ADV_ABILITY_FULLDUPLEX BIT(12)
> +#define MAC2MAC_MR_ADV_ABILITY_1G BIT(11)
> +#define MAC2MAC_MR_ADV_ABILITY_100M BIT(10)
> +#define MAC2PHY_MR_ADV_ABILITY BIT(0)
Most of the above don't seem to be used, and the only one that seems to
be used is used in a variable declaration where the variable isn't used,
and thus us also unused.
>
> #define AM65_CPSW_CTL_VLAN_AWARE BIT(1)
> #define AM65_CPSW_CTL_P0_ENABLE BIT(2)
> @@ -1493,6 +1501,7 @@ static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned in
> struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data,
> phylink_config);
> struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave);
> + u32 mr_adv_ability = MAC2MAC_MR_ADV_ABILITY_BASE;
This doesn't seem to be used; should it be part of a different patch?
I get the impression that most of this patch should be elsewhere in this
series.
> struct am65_cpsw_common *common = port->common;
> struct fwnode_handle *fwnode;
> bool fixed_link = false;
> @@ -2105,8 +2114,12 @@ am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx)
> __set_bit(PHY_INTERFACE_MODE_RMII,
> port->slave.phylink_config.supported_interfaces);
> } else if (common->pdata.extra_modes & BIT(port->slave.phy_if)) {
> - __set_bit(PHY_INTERFACE_MODE_QSGMII,
> - port->slave.phylink_config.supported_interfaces);
> + if (port->slave.phy_if == PHY_INTERFACE_MODE_QSGMII)
> + __set_bit(PHY_INTERFACE_MODE_QSGMII,
> + port->slave.phylink_config.supported_interfaces);
> + else
> + __set_bit(PHY_INTERFACE_MODE_SGMII,
> + port->slave.phylink_config.supported_interfaces);
> } else {
> dev_err(dev, "selected phy-mode is not supported\n");
> return -EOPNOTSUPP;
> @@ -2744,7 +2757,7 @@ static const struct am65_cpsw_pdata j7200_cpswxg_pdata = {
> .quirks = 0,
> .ale_dev_id = "am64-cpswxg",
> .fdqring_mode = K3_RINGACC_RING_MODE_RING,
> - .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII),
> + .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII),
> };
>
> static const struct of_device_id am65_cpsw_nuss_of_mtable[] = {
> --
> 2.25.1
>
>
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
Hello Russell, On 14/09/22 21:14, Russell King (Oracle) wrote: > On Wed, Sep 14, 2022 at 03:20:51PM +0530, Siddharth Vadapalli wrote: >> Add support for SGMII mode in both fixed-link MAC2MAC master mode and >> MAC2PHY modes for CPSW5G ports. >> >> Add SGMII mode to the list of extra_modes in j7200_cpswxg_pdata. >> >> The MAC2PHY mode has been tested in fixed-link mode using a bootstrapped >> PHY. The MAC2MAC mode has been tested by a customer with J7200 SoC on >> their device. >> >> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> >> --- >> drivers/net/ethernet/ti/am65-cpsw-nuss.c | 19 ++++++++++++++++--- >> 1 file changed, 16 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c >> index 1739c389af20..3f40178436ff 100644 >> --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c >> +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c >> @@ -75,7 +75,15 @@ >> #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 0x31C >> >> #define AM65_CPSW_SGMII_CONTROL_REG 0x010 >> +#define AM65_CPSW_SGMII_MR_ADV_ABILITY_REG 0x018 > > This doesn't seem to be used in this patch, should it be part of some > other patch in the series? > >> #define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE BIT(0) >> +#define AM65_CPSW_SGMII_CONTROL_MASTER_MODE BIT(5) > > Ditto. > >> + >> +#define MAC2MAC_MR_ADV_ABILITY_BASE (BIT(15) | BIT(0)) >> +#define MAC2MAC_MR_ADV_ABILITY_FULLDUPLEX BIT(12) >> +#define MAC2MAC_MR_ADV_ABILITY_1G BIT(11) >> +#define MAC2MAC_MR_ADV_ABILITY_100M BIT(10) >> +#define MAC2PHY_MR_ADV_ABILITY BIT(0) > > Most of the above don't seem to be used, and the only one that seems to > be used is used in a variable declaration where the variable isn't used, > and thus us also unused. > >> >> #define AM65_CPSW_CTL_VLAN_AWARE BIT(1) >> #define AM65_CPSW_CTL_P0_ENABLE BIT(2) >> @@ -1493,6 +1501,7 @@ static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned in >> struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, >> phylink_config); >> struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); >> + u32 mr_adv_ability = MAC2MAC_MR_ADV_ABILITY_BASE; > > This doesn't seem to be used; should it be part of a different patch? > > I get the impression that most of this patch should be elsewhere in this > series. Thank you for pointing it out. These should have been a part of the previous patch [PATCH 5/8]. Sorry for the confusion. I will fix this in the v2 series. Regards, Siddharth.
On Wed, Sep 14, 2022 at 03:20:51PM +0530, Siddharth Vadapalli wrote: > +#define MAC2MAC_MR_ADV_ABILITY_BASE (BIT(15) | BIT(0)) > +#define MAC2MAC_MR_ADV_ABILITY_FULLDUPLEX BIT(12) > +#define MAC2MAC_MR_ADV_ABILITY_1G BIT(11) > +#define MAC2MAC_MR_ADV_ABILITY_100M BIT(10) > +#define MAC2PHY_MR_ADV_ABILITY BIT(0) In addition to my other comments, this looks like a reimplementation of the LPA_SGMII* constants found in include/uapi/linux/mii.h -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
Hello Russell, On 14/09/22 21:34, Russell King (Oracle) wrote: > On Wed, Sep 14, 2022 at 03:20:51PM +0530, Siddharth Vadapalli wrote: >> +#define MAC2MAC_MR_ADV_ABILITY_BASE (BIT(15) | BIT(0)) >> +#define MAC2MAC_MR_ADV_ABILITY_FULLDUPLEX BIT(12) >> +#define MAC2MAC_MR_ADV_ABILITY_1G BIT(11) >> +#define MAC2MAC_MR_ADV_ABILITY_100M BIT(10) >> +#define MAC2PHY_MR_ADV_ABILITY BIT(0) > > In addition to my other comments, this looks like a reimplementation of > the LPA_SGMII* constants found in include/uapi/linux/mii.h I was not aware of this. Thank you for letting me know. I will use the existing constants in the v2 series. Regards, Siddharth.
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