This patchset adds PTP support for CN10K silicon, specifically
to workaround few hardware issues and to add 1-step mode.

Patchset overview:

Patch #1 returns correct ptp timestamp in nanoseconds captured
         when external timestamp event occurs.

Patch #2 adds 1-step mode support.

Patch #3 implements software workaround to generate PPS output properly.

Patch #4 provides a software workaround for the rollover register default
         value, which causes ptp to return the wrong timestamp.

Hariprasad Kelam (1):
  octeontx2-pf: Add support for ptp 1-step mode on CN10K silicon

Naveen Mamindlapalli (3):
  octeontx2-af: return correct ptp timestamp for CN10K silicon
  octeontx2-af: Add PTP PPS Errata workaround on CN10K silicon
  octeontx2-af: Initialize PTP_SEC_ROLLOVER register properly

 drivers/net/ethernet/marvell/octeontx2/af/mbox.h   |   2 +
 drivers/net/ethernet/marvell/octeontx2/af/ptp.c    | 106 +++++++++++++++++++-
 drivers/net/ethernet/marvell/octeontx2/af/ptp.h    |   3 +
 drivers/net/ethernet/marvell/octeontx2/af/rpm.c    |  19 +++-
 drivers/net/ethernet/marvell/octeontx2/af/rpm.h    |   5 +
 .../net/ethernet/marvell/octeontx2/af/rvu_nix.c    |   8 +-
 .../net/ethernet/marvell/octeontx2/af/rvu_reg.h    |   1 +
 .../ethernet/marvell/octeontx2/nic/otx2_common.h   |  13 +++
 .../ethernet/marvell/octeontx2/nic/otx2_ethtool.c  |   8 +-
 .../net/ethernet/marvell/octeontx2/nic/otx2_pf.c   |  11 +++
 .../net/ethernet/marvell/octeontx2/nic/otx2_ptp.c  | 103 ++++++++++++++-----
 .../ethernet/marvell/octeontx2/nic/otx2_struct.h   |  11 ++-
 .../net/ethernet/marvell/octeontx2/nic/otx2_txrx.c | 110 ++++++++++++++++++++-
 13 files changed, 359 insertions(+), 41 deletions(-)

-- 
2.16.5

On Sat, Sep 10, 2022 at 01:24:12PM +0530, Naveen Mamindlapalli wrote:
> This patchset adds PTP support for CN10K silicon, specifically
> to workaround few hardware issues and to add 1-step mode.
> 
> Patchset overview:
> 
> Patch #1 returns correct ptp timestamp in nanoseconds captured
>          when external timestamp event occurs.
> 
> Patch #2 adds 1-step mode support.
> 
> Patch #3 implements software workaround to generate PPS output properly.
> 
> Patch #4 provides a software workaround for the rollover register default
>          value, which causes ptp to return the wrong timestamp.
> 
> Hariprasad Kelam (1):
>   octeontx2-pf: Add support for ptp 1-step mode on CN10K silicon
> 
> Naveen Mamindlapalli (3):
>   octeontx2-af: return correct ptp timestamp for CN10K silicon
>   octeontx2-af: Add PTP PPS Errata workaround on CN10K silicon
>   octeontx2-af: Initialize PTP_SEC_ROLLOVER register properly

For the series:

Acked-by: Richard Cochran <richardcochran@gmail.com>

Hello:

This series was applied to netdev/net-next.git (master)
by David S. Miller <davem@davemloft.net>:

On Sat, 10 Sep 2022 13:24:12 +0530 you wrote:
> This patchset adds PTP support for CN10K silicon, specifically
> to workaround few hardware issues and to add 1-step mode.
> 
> Patchset overview:
> 
> Patch #1 returns correct ptp timestamp in nanoseconds captured
>          when external timestamp event occurs.
> 
> [...]

Here is the summary with links:
  - [net-next,1/4] octeontx2-af: return correct ptp timestamp for CN10K silicon
    https://git.kernel.org/netdev/net-next/c/a8025e7946a2
  - [net-next,2/4] octeontx2-pf: Add support for ptp 1-step mode on CN10K silicon
    https://git.kernel.org/netdev/net-next/c/2958d17a8984
  - [net-next,3/4] octeontx2-af: Add PTP PPS Errata workaround on CN10K silicon
    https://git.kernel.org/netdev/net-next/c/2ef4e45d99b1
  - [net-next,4/4] octeontx2-af: Initialize PTP_SEC_ROLLOVER register properly
    https://git.kernel.org/netdev/net-next/c/85a5f9638313

You are awesome, thank you!
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