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[PATCH v2 3/6] soc: sifive: ccache: determine the cache level from dts

Zong Li posted 6 patches 3 years, 7 months ago
There is a newer version of this series
[PATCH v2 3/6] soc: sifive: ccache: determine the cache level from dts
Posted by Zong Li 3 years, 7 months ago 
Composable cache could be L2 or L3 cache, use 'cache-level' property of
device node to determine the level.

Signed-off-by: Zong Li <zong.li@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
---
 drivers/soc/sifive/sifive_ccache.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
index 1b16a196547f..0e0eb85c94d8 100644
--- a/drivers/soc/sifive/sifive_ccache.c
+++ b/drivers/soc/sifive/sifive_ccache.c
@@ -38,6 +38,7 @@
 static void __iomem *ccache_base;
 static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR];
 static struct riscv_cacheinfo_ops ccache_cache_ops;
+static int level;
 
 enum {
 	DIR_CORR = 0,
@@ -143,7 +144,7 @@ static const struct attribute_group priv_attr_group = {
 static const struct attribute_group *ccache_get_priv_group(struct cacheinfo *this_leaf)
 {
 	/* We want to use private group for composable cache only */
-	if (this_leaf->level == 2)
+	if (this_leaf->level == level)
 		return &priv_attr_group;
 	else
 		return NULL;
@@ -210,6 +211,9 @@ static int __init sifive_ccache_init(void)
 	if (!ccache_base)
 		return -ENOMEM;
 
+	if (of_property_read_u32(np, "cache-level", &level))
+		return -ENODEV;
+
 	intr_num = of_property_count_u32_elems(np, "interrupts");
 	if (!intr_num) {
 		pr_err("CCACHE: no interrupts property\n");
-- 
2.17.1
Re: [PATCH v2 3/6] soc: sifive: ccache: determine the cache level from dts
Posted by Conor.Dooley@microchip.com 3 years, 7 months ago 
On 05/09/2022 09:31, Zong Li wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Composable cache could be L2 or L3 cache, use 'cache-level' property of
> device node to determine the level.
> 
> Signed-off-by: Zong Li <zong.li@sifive.com>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> ---
>  drivers/soc/sifive/sifive_ccache.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> index 1b16a196547f..0e0eb85c94d8 100644
> --- a/drivers/soc/sifive/sifive_ccache.c
> +++ b/drivers/soc/sifive/sifive_ccache.c
> @@ -38,6 +38,7 @@
>  static void __iomem *ccache_base;
>  static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR];
>  static struct riscv_cacheinfo_ops ccache_cache_ops;
> +static int level;

Can you have a system with a composable l2 & l3 cache?

> 
>  enum {
>         DIR_CORR = 0,
> @@ -143,7 +144,7 @@ static const struct attribute_group priv_attr_group = {
>  static const struct attribute_group *ccache_get_priv_group(struct cacheinfo *this_leaf)
>  {
>         /* We want to use private group for composable cache only */
> -       if (this_leaf->level == 2)
> +       if (this_leaf->level == level)
>                 return &priv_attr_group;
>         else
>                 return NULL;
> @@ -210,6 +211,9 @@ static int __init sifive_ccache_init(void)
>         if (!ccache_base)
>                 return -ENOMEM;
> 
> +       if (of_property_read_u32(np, "cache-level", &level))
> +               return -ENODEV;
> +
>         intr_num = of_property_count_u32_elems(np, "interrupts");
>         if (!intr_num) {
>                 pr_err("CCACHE: no interrupts property\n");
> --
> 2.17.1
>
Re: [PATCH v2 3/6] soc: sifive: ccache: determine the cache level from dts
Posted by Zong Li 3 years, 7 months ago 
<Conor.Dooley@microchip.com> 於 2022年9月6日 週二 凌晨2:56寫道：
>
> On 05/09/2022 09:31, Zong Li wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > Composable cache could be L2 or L3 cache, use 'cache-level' property of
> > device node to determine the level.
> >
> > Signed-off-by: Zong Li <zong.li@sifive.com>
> > Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> > ---
> >  drivers/soc/sifive/sifive_ccache.c | 6 +++++-
> >  1 file changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> > index 1b16a196547f..0e0eb85c94d8 100644
> > --- a/drivers/soc/sifive/sifive_ccache.c
> > +++ b/drivers/soc/sifive/sifive_ccache.c
> > @@ -38,6 +38,7 @@
> >  static void __iomem *ccache_base;
> >  static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR];
> >  static struct riscv_cacheinfo_ops ccache_cache_ops;
> > +static int level;
>
> Can you have a system with a composable l2 & l3 cache?

We don't have a system with composable L2 and L3 cache at same time.
But as I mentioned in the thread of second patch, we use another cache
as L2 when the composable cache used for L3.

>
> >
> >  enum {
> >         DIR_CORR = 0,
> > @@ -143,7 +144,7 @@ static const struct attribute_group priv_attr_group = {
> >  static const struct attribute_group *ccache_get_priv_group(struct cacheinfo *this_leaf)
> >  {
> >         /* We want to use private group for composable cache only */
> > -       if (this_leaf->level == 2)
> > +       if (this_leaf->level == level)
> >                 return &priv_attr_group;
> >         else
> >                 return NULL;
> > @@ -210,6 +211,9 @@ static int __init sifive_ccache_init(void)
> >         if (!ccache_base)
> >                 return -ENOMEM;
> >
> > +       if (of_property_read_u32(np, "cache-level", &level))
> > +               return -ENODEV;
> > +
> >         intr_num = of_property_count_u32_elems(np, "interrupts");
> >         if (!intr_num) {
> >                 pr_err("CCACHE: no interrupts property\n");
> > --
> > 2.17.1
> >
>

Patchew 2.1-devel-ea86937

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