On 9/3/22 02:22, Sean Christopherson wrote:
> Purge the "highest ISR" cache when updating APICv state on a vCPU. The
> cache must not be used when APICv is active as hardware may emulate EOIs
> (and other operations) without exiting to KVM.
>
> This fixes a bug where KVM will effectively block IRQs in perpetuity due
> to the "highest ISR" never getting reset if APICv is activated on a vCPU
> while an IRQ is in-service. Hardware emulates the EOI and KVM never gets
> a chance to update its cache.
>
> Fixes: b26a695a1d78 ("kvm: lapic: Introduce APICv update helper function")
> Cc: stable@vger.kernel.org
> Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
> Cc: Maxim Levitsky <mlevitsk@redhat.com>
> Signed-off-by: Sean Christopherson <seanjc@google.com>
> ---
> arch/x86/kvm/lapic.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> index 9dda989a1cf0..38e9b8e5278c 100644
> --- a/arch/x86/kvm/lapic.c
> +++ b/arch/x86/kvm/lapic.c
> @@ -2429,6 +2429,7 @@ void kvm_apic_update_apicv(struct kvm_vcpu *vcpu)
> */
> apic->isr_count = count_vectors(apic->regs + APIC_ISR);
> }
> + apic->highest_isr_cache = -1;
> }
> EXPORT_SYMBOL_GPL(kvm_apic_update_apicv);
>
> @@ -2485,7 +2486,6 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
> kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
> }
> kvm_apic_update_apicv(vcpu);
> - apic->highest_isr_cache = -1;
> update_divide_count(apic);
> atomic_set(&apic->lapic_timer.pending, 0);
>
> @@ -2772,7 +2772,6 @@ int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
> __start_apic_timer(apic, APIC_TMCCT);
> kvm_lapic_set_reg(apic, APIC_TMCCT, 0);
> kvm_apic_update_apicv(vcpu);
> - apic->highest_isr_cache = -1;
> if (apic->apicv_active) {
> static_call_cond(kvm_x86_apicv_post_state_restore)(vcpu);
> static_call_cond(kvm_x86_hwapic_irr_update)(vcpu, apic_find_highest_irr(apic));
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>