EDAC: Improve memory address decoding for i10nm driver

[PATCH 0/3] EDAC: Improve memory address decoding for i10nm driver

Tony Luck posted 3 patches 3 years, 7 months ago

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arch/x86/include/asm/mce.h |   1 +
drivers/edac/skx_common.h  |   6 ++
drivers/edac/i10nm_base.c  | 134 ++++++++++++++++++++++++++++++++++++-
drivers/edac/skx_base.c    |   9 ++-
drivers/edac/skx_common.c  |  21 +++---
5 files changed, 158 insertions(+), 13 deletions(-)

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[PATCH 0/3] EDAC: Improve memory address decoding for i10nm driver

Posted by Tony Luck 3 years, 7 months ago

Calling firmware to translate memory addresses has a high impact
on system because the call uses SMI.

The 10nm server processors (Icelake and Tremont) provide additional
information in the IA32_MCi_MISC registers that can be used to decode
the address of an error in DDR memory.

Couple of prep patches before the main event in part 3 that decodes
the address from the MISC register.

Qiuxu Zhuo (2):
  EDAC/skx_common: Use driver decoder first
  EDAC/skx_common: Make output format similar

Youquan Song (1):
  EDAC/i10nm: Add driver decoder for Ice Lake and Tremont CPUs

 arch/x86/include/asm/mce.h |   1 +
 drivers/edac/skx_common.h  |   6 ++
 drivers/edac/i10nm_base.c  | 134 ++++++++++++++++++++++++++++++++++++-
 drivers/edac/skx_base.c    |   9 ++-
 drivers/edac/skx_common.c  |  21 +++---
 5 files changed, 158 insertions(+), 13 deletions(-)


base-commit: b90cb1053190353cc30f0fef0ef1f378ccc063c5
-- 
2.37.1