.../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
From: "Jason-JH.Lin" <jason-jh.lin@mediatek.com>
For previous MediaTek SoCs, such as MT8173, there are 2 display HW
pipelines binding to 1 mmsys with the same power domain, the same
clock driver and the same mediatek-drm driver.
For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
2 different power domains, different clock drivers and different
mediatek-drm drivers.
Therefore, we need to separate these two different mmsys hardwares to
2 different compatibles for MT8195.
Fixes: 81c5a41d10b9 ("dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding")
Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
---
.../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 6ad023eec193..bfbdd30d2092 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -31,7 +31,8 @@ properties:
- mediatek,mt8183-mmsys
- mediatek,mt8186-mmsys
- mediatek,mt8192-mmsys
- - mediatek,mt8195-mmsys
+ - mediatek,mt8195-vdosys0
+ - mediatek,mt8195-vdosys1
- mediatek,mt8365-mmsys
- const: syscon
- items:
--
2.18.0
On 25/08/2022 07:56, Bo-Chen Chen wrote:
> From: "Jason-JH.Lin" <jason-jh.lin@mediatek.com>
>
> For previous MediaTek SoCs, such as MT8173, there are 2 display HW
> pipelines binding to 1 mmsys with the same power domain, the same
> clock driver and the same mediatek-drm driver.
>
> For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
> 2 different power domains, different clock drivers and different
> mediatek-drm drivers.
>
> Therefore, we need to separate these two different mmsys hardwares to
> 2 different compatibles for MT8195.
>
> Fixes: 81c5a41d10b9 ("dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding")
> Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
> Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
> ---
> .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> index 6ad023eec193..bfbdd30d2092 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> @@ -31,7 +31,8 @@ properties:
> - mediatek,mt8183-mmsys
> - mediatek,mt8186-mmsys
> - mediatek,mt8192-mmsys
> - - mediatek,mt8195-mmsys
> + - mediatek,mt8195-vdosys0
> + - mediatek,mt8195-vdosys1
If I understand correctly support for vdosys0 is merged with the old compatible.
We should therefore keep mediatek,mt8195-mmsys as a fallback for
mediatek,mt8195-vdosys0.
Regards,
Matthias
> - mediatek,mt8365-mmsys
> - const: syscon
> - items:
On 25/08/2022 08:56, Bo-Chen Chen wrote: > From: "Jason-JH.Lin" <jason-jh.lin@mediatek.com> > > For previous MediaTek SoCs, such as MT8173, there are 2 display HW > pipelines binding to 1 mmsys with the same power domain, the same > clock driver and the same mediatek-drm driver. > > For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to > 2 different power domains, different clock drivers and different > mediatek-drm drivers. I don't see binding to different clock drivers and anyway that's not really an argument here. Please focus in description on hardware properties, IOW, are devices compatible or different. What is the incompatible difference between VDOSYS0 and 1? Best regards, Krzysztof
On Thu, 2022-08-25 at 14:11 +0800, Krzysztof Kozlowski wrote: > On 25/08/2022 08:56, Bo-Chen Chen wrote: > > From: "Jason-JH.Lin" <jason-jh.lin@mediatek.com> > > > > For previous MediaTek SoCs, such as MT8173, there are 2 display HW > > pipelines binding to 1 mmsys with the same power domain, the same > > clock driver and the same mediatek-drm driver. > > > > For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding > > to > > 2 different power domains, different clock drivers and different > > mediatek-drm drivers. > > I don't see binding to different clock drivers and anyway that's not > really an argument here. Please focus in description on hardware > properties, IOW, are devices compatible or different. What is the > incompatible difference between VDOSYS0 and 1? > > Best regards, > Krzysztof Hello Krzysztof, Thanks for yor review. From the functions perspective: Hardware pipeline of VDOSYS0 has these components: COLOR, CCORR, AAL, GAMMA, DITHER. They are related to PQ (Picture Quality) functions and they makes VDOSYS0 supports PQ function while they are not including in VDOSYS1. Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related component). It makes VDOSYS1 supports the HDR function while it's not including in VDOSYS0. About mediatek ETHDR, you can refer to this series: https://lore.kernel.org/all/20220819061456.8042-2-nancy.lin@mediatek.com/ To summary: Only VDOSYS0 can support PQ adjustment. Only VDOSYS1 can support HDR adjustment. Is this description ok for you? If it is ok, I will put them into commit message in next version. BRs, Bo-Chen
On 25/08/2022 08:59, Bo-Chen Chen wrote: > On Thu, 2022-08-25 at 14:11 +0800, Krzysztof Kozlowski wrote: >> On 25/08/2022 08:56, Bo-Chen Chen wrote: >>> From: "Jason-JH.Lin" <jason-jh.lin@mediatek.com> >>> >>> For previous MediaTek SoCs, such as MT8173, there are 2 display HW >>> pipelines binding to 1 mmsys with the same power domain, the same >>> clock driver and the same mediatek-drm driver. >>> >>> For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding >>> to >>> 2 different power domains, different clock drivers and different >>> mediatek-drm drivers. drop clock driver example here. >> >> I don't see binding to different clock drivers and anyway that's not >> really an argument here. Please focus in description on hardware >> properties, IOW, are devices compatible or different. What is the >> incompatible difference between VDOSYS0 and 1? >> >> Best regards, >> Krzysztof > > Hello Krzysztof, > > Thanks for yor review. > > From the functions perspective: > > Hardware pipeline of VDOSYS0 has these components: COLOR, CCORR, AAL, > GAMMA, DITHER. > They are related to PQ (Picture Quality) functions and they makes > VDOSYS0 supports PQ function while they are not including in VDOSYS1. > > Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related > component). > It makes VDOSYS1 supports the HDR function while it's not including in > VDOSYS0. > Please include a description of this in the commit message. > About mediatek ETHDR, you can refer to this series: > > https://lore.kernel.org/all/20220819061456.8042-2-nancy.lin@mediatek.com/ > > To summary: > Only VDOSYS0 can support PQ adjustment. > Only VDOSYS1 can support HDR adjustment. > > Is this description ok for you? > If it is ok, I will put them into commit message in next version. > > BRs, > Bo-Chen >
On Thu, 2022-08-25 at 18:55 +0800, Matthias Brugger wrote: > > On 25/08/2022 08:59, Bo-Chen Chen wrote: > > On Thu, 2022-08-25 at 14:11 +0800, Krzysztof Kozlowski wrote: > > > On 25/08/2022 08:56, Bo-Chen Chen wrote: > > > > From: "Jason-JH.Lin" <jason-jh.lin@mediatek.com> > > > > > > > > For previous MediaTek SoCs, such as MT8173, there are 2 display > > > > HW > > > > pipelines binding to 1 mmsys with the same power domain, the > > > > same > > > > clock driver and the same mediatek-drm driver. > > > > > > > > For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines > > > > binding > > > > to > > > > 2 different power domains, different clock drivers and > > > > different > > > > mediatek-drm drivers. > > drop clock driver example here. > Hello Matthias, Thanks for your review. I am not sure what do you mean. Could you explain more detailedly? > > > > > > I don't see binding to different clock drivers and anyway that's > > > not > > > really an argument here. Please focus in description on hardware > > > properties, IOW, are devices compatible or different. What is the > > > incompatible difference between VDOSYS0 and 1? > > > > > > Best regards, > > > Krzysztof > > > > Hello Krzysztof, > > > > Thanks for yor review. > > > > From the functions perspective: > > > > Hardware pipeline of VDOSYS0 has these components: COLOR, CCORR, > > AAL, > > GAMMA, DITHER. > > They are related to PQ (Picture Quality) functions and they makes > > VDOSYS0 supports PQ function while they are not including in > > VDOSYS1. > > > > Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related > > component). > > It makes VDOSYS1 supports the HDR function while it's not including > > in > > VDOSYS0. > > > > Please include a description of this in the commit message. > Yes, I have sent v2 and add these to commit meesage. https://lore.kernel.org/all/20220825091448.14008-1-rex-bc.chen@mediatek.com/ BRs, Bo-chen > > About mediatek ETHDR, you can refer to this series: > > > > https://lore.kernel.org/all/20220819061456.8042-2-nancy.lin@mediatek.com/ > > > > To summary: > > Only VDOSYS0 can support PQ adjustment. > > Only VDOSYS1 can support HDR adjustment. > > > > Is this description ok for you? > > If it is ok, I will put them into commit message in next version. > > > > BRs, > > Bo-Chen > >
On 25/08/2022 13:06, Bo-Chen Chen wrote: > On Thu, 2022-08-25 at 18:55 +0800, Matthias Brugger wrote: >> >> On 25/08/2022 08:59, Bo-Chen Chen wrote: >>> On Thu, 2022-08-25 at 14:11 +0800, Krzysztof Kozlowski wrote: >>>> On 25/08/2022 08:56, Bo-Chen Chen wrote: >>>>> From: "Jason-JH.Lin" <jason-jh.lin@mediatek.com> >>>>> >>>>> For previous MediaTek SoCs, such as MT8173, there are 2 display >>>>> HW >>>>> pipelines binding to 1 mmsys with the same power domain, the >>>>> same >>>>> clock driver and the same mediatek-drm driver. >>>>> >>>>> For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines >>>>> binding >>>>> to >>>>> 2 different power domains, different clock drivers and >>>>> different >>>>> mediatek-drm drivers. >> >> drop clock driver example here. >> > > Hello Matthias, > > Thanks for your review. > I am not sure what do you mean. > Could you explain more detailedly? > Never mind, it's not that important. Regards, Matthias >>>> >>>> I don't see binding to different clock drivers and anyway that's >>>> not >>>> really an argument here. Please focus in description on hardware >>>> properties, IOW, are devices compatible or different. What is the >>>> incompatible difference between VDOSYS0 and 1? >>>> >>>> Best regards, >>>> Krzysztof >>> >>> Hello Krzysztof, >>> >>> Thanks for yor review. >>> >>> From the functions perspective: >>> >>> Hardware pipeline of VDOSYS0 has these components: COLOR, CCORR, >>> AAL, >>> GAMMA, DITHER. >>> They are related to PQ (Picture Quality) functions and they makes >>> VDOSYS0 supports PQ function while they are not including in >>> VDOSYS1. >>> >>> Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related >>> component). >>> It makes VDOSYS1 supports the HDR function while it's not including >>> in >>> VDOSYS0. >>> >> >> Please include a description of this in the commit message. >> > > Yes, I have sent v2 and add these to commit meesage. > > https://lore.kernel.org/all/20220825091448.14008-1-rex-bc.chen@mediatek.com/ > > BRs, > Bo-chen > >>> About mediatek ETHDR, you can refer to this series: >>> >>> > https://lore.kernel.org/all/20220819061456.8042-2-nancy.lin@mediatek.com/ >>> >>> To summary: >>> Only VDOSYS0 can support PQ adjustment. >>> Only VDOSYS1 can support HDR adjustment. >>> >>> Is this description ok for you? >>> If it is ok, I will put them into commit message in next version. >>> >>> BRs, >>> Bo-Chen >>> >
On 25/08/2022 09:59, Bo-Chen Chen wrote: > > Hello Krzysztof, > > Thanks for yor review. > > From the functions perspective: > > Hardware pipeline of VDOSYS0 has these components: COLOR, CCORR, AAL, > GAMMA, DITHER. > They are related to PQ (Picture Quality) functions and they makes > VDOSYS0 supports PQ function while they are not including in VDOSYS1. > > Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related > component). > It makes VDOSYS1 supports the HDR function while it's not including in > VDOSYS0. > > About mediatek ETHDR, you can refer to this series: > > https://lore.kernel.org/all/20220819061456.8042-2-nancy.lin@mediatek.com/ > > To summary: > Only VDOSYS0 can support PQ adjustment. > Only VDOSYS1 can support HDR adjustment. > > Is this description ok for you? > If it is ok, I will put them into commit message in next version. > Yes. Best regards, Krzysztof
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