RZ/Five SoC is pin compatible with RZ/G2UL (Type 1) SoC. This patch
updates the comment to include RZ/Five SoC so that we make it clear
"renesas,r9a07g043-pinctrl" compatible string will be used for RZ/Five
SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml      | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index 997b74639112..f081acb7ba04 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -23,7 +23,7 @@ properties:
     oneOf:
       - items:
           - enum:
-              - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2}
+              - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
               - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
 
       - items:
-- 
2.17.1

On Tue, Jul 26, 2022 at 7:53 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> RZ/Five SoC is pin compatible with RZ/G2UL (Type 1) SoC. This patch
> updates the comment to include RZ/Five SoC so that we make it clear
> "renesas,r9a07g043-pinctrl" compatible string will be used for RZ/Five
> SoC.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-pinctrl-for-v6.1.

> --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> @@ -23,7 +23,7 @@ properties:
>      oneOf:
>        - items:
>            - enum:
> -              - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2}
> +              - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
>                - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
>
>        - items:

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

On Tue, Jul 26, 2022 at 06:53:15PM +0100, Lad Prabhakar wrote:
> RZ/Five SoC is pin compatible with RZ/G2UL (Type 1) SoC. This patch
> updates the comment to include RZ/Five SoC so that we make it clear
> "renesas,r9a07g043-pinctrl" compatible string will be used for RZ/Five
> SoC.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  .../devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml      | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Same comments as here[1].

Rob

[1] https://lore.kernel.org/all/20220727153738.GA2696116-robh@kernel.org/

Hi Rob,

Thank you for the review.

On Wed, Jul 27, 2022 at 4:40 PM Rob Herring <robh@kernel.org> wrote:
>
> On Tue, Jul 26, 2022 at 06:53:15PM +0100, Lad Prabhakar wrote:
> > RZ/Five SoC is pin compatible with RZ/G2UL (Type 1) SoC. This patch
> > updates the comment to include RZ/Five SoC so that we make it clear
> > "renesas,r9a07g043-pinctrl" compatible string will be used for RZ/Five
> > SoC.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> >  .../devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml      | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
>
> Same comments as here[1].
>
This block is identical on RZ/G2UL and RZ/Five SoC.

> Rob
>
> [1] https://lore.kernel.org/all/20220727153738.GA2696116-robh@kernel.org/

Cheers,
Prabhakar