.../renesas,rzg2l-irqc.yaml | 133 ++++++ .../pinctrl/renesas,rzg2l-pinctrl.yaml | 15 + drivers/gpio/gpiolib.c | 9 +- drivers/irqchip/Kconfig | 8 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-renesas-rzg2l.c | 393 ++++++++++++++++++ drivers/pinctrl/renesas/pinctrl-rzg2l.c | 233 +++++++++++ 7 files changed, 789 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml create mode 100644 drivers/irqchip/irq-renesas-rzg2l.c
Hi All,
The RZ/G2L Interrupt Controller is a front-end for the GIC found on
Renesas RZ/G2L SoC's with below pins:
- IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI
interrupts
- GPIO pins used as external interrupt input pins out of GPIOINT0-122 a
maximum of only 32 can be mapped to 32 GIC SPI interrupts,
- NMI edge select.
_____________
| GIC |
| ________ |
____________ | | | |
NMI --------------------------------->| | SPI0-479 | | GIC-600| |
_______ | |------------>| | |
| | | | PPI16-31 | | | |
| | IRQ0-IRQ7 | IRQC |------------>| | |
P0_P48_4 --->| GPIO |---------------->| | | |________| |
| |GPIOINT0-122 | | | |
| |---------------->| TINT0-31 | | |
|______| |__________| |____________|
The proposed patches add hierarchical IRQ domain, one in IRQC driver and
another in pinctrl driver. Upon interrupt requests map the interrupt to
GIC. Out of GPIOINT0-122 only 32 can be mapped to GIC SPI, this mapping is
handled by the pinctrl and IRQC driver.
Cheers,
Prabhakar
v6->v7:
* Used devm_reset_control_get_exclusive() instead of
devm_reset_control_get_exclusive_by_index()
* Included RB tag from Linus for patch 5/5
* Switched to newer version of populate_parent_alloc_arg() (patch depends
on https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git/
patch/?id=178b7e21459e9a7e2a2c369711ef0cc9b1cfbcd7)
v5->v6:
* Fixed review comments pointed by Marc
* Included Ack from Rob
v4->v5:
* Updated commit message for patch 3/5
* Dropped interrupt-parent from and included RB tag from Geert
for patch 4/5
* Implemented init_valid_mask() callback
* Dropped ngirq patch from previous series
* Dropped patches 4/7 and 5/7 from previous patch series will handle
it separately.
v3->v4:
* Updated description for interrupts-cells property in patch #1
* Dropped the patch which overriding free callback in gpiolib
* Used devm helpers in patch#2
* Patch #4, #5 and #6 are newly added
* In patch #7 dropped using gpio offset as hwirq
* Implemented immutable GPIO in patch #7
* Implemented child_offset_to_irq() callback in patch #7
v2->v3:
* Updated description for interrupts-cells property in patch #1
* Included RB tag from Geert for binding patch
* Fixed review comments pointed by Geert, Biju and Sergei.
v1->v2:
* Included RB tag from Rob
* Fixed review comments pointed by Geert
* included GPIO driver changes
RFCV4 -> V1:
* Used unevaluatedProperties.
* Altered the sequence of reg property
* Set the parent type
* Used raw_spin_lock() instead of raw_spin_lock_irqsave()
* Simplified parsing IRQ map.
* Will send the GPIO and pinctrl changes as part of separate series
RFC v4:
* Used locking while RMW
* Now using interrupts property instead of interrupt-map
* Patch series depends on [0]
* Updated binding doc
* Fixed comments pointed by Andy
[0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
20220316200633.28974-1-prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx/
RFC v3:
-> Re-structured the driver as a hierarchical irq domain instead of chained
-> made use of IRQCHIP_* macros
-> dropped locking
-> Added support for IRQ0-7 interrupts
-> Introduced 2 new patches for GPIOLIB
-> Switched to using GPIOLIB for irqdomains in pinctrl
RFC v2: https://patchwork.kernel.org/project/linux-renesas-soc/cover/
20210921193028.13099-1-prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx/
RFC v1: https://patchwork.kernel.org/project/linux-renesas-soc/cover/
20210803175109.1729-1-prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx/
Lad Prabhakar (5):
dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt
Controller
irqchip: Add RZ/G2L IA55 Interrupt Controller driver
gpio: gpiolib: Allow free() callback to be overridden
dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Document the properties
to handle GPIO IRQ
pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to handle GPIO
interrupt
.../renesas,rzg2l-irqc.yaml | 133 ++++++
.../pinctrl/renesas,rzg2l-pinctrl.yaml | 15 +
drivers/gpio/gpiolib.c | 9 +-
drivers/irqchip/Kconfig | 8 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-renesas-rzg2l.c | 393 ++++++++++++++++++
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 233 +++++++++++
7 files changed, 789 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
create mode 100644 drivers/irqchip/irq-renesas-rzg2l.c
--
2.25.1
On Sun, 03 Jul 2022 20:40:15 +0100, Lad Prabhakar <prabhakar.csengg@gmail.com> wrote: > > Hi All, > > The RZ/G2L Interrupt Controller is a front-end for the GIC found on > Renesas RZ/G2L SoC's with below pins: > - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI > interrupts > - GPIO pins used as external interrupt input pins out of GPIOINT0-122 a > maximum of only 32 can be mapped to 32 GIC SPI interrupts, > - NMI edge select. > > _____________ > | GIC | > | ________ | > ____________ | | | | > NMI --------------------------------->| | SPI0-479 | | GIC-600| | > _______ | |------------>| | | > | | | | PPI16-31 | | | | > | | IRQ0-IRQ7 | IRQC |------------>| | | > P0_P48_4 --->| GPIO |---------------->| | | |________| | > | |GPIOINT0-122 | | | | > | |---------------->| TINT0-31 | | | > |______| |__________| |____________| > > The proposed patches add hierarchical IRQ domain, one in IRQC driver and > another in pinctrl driver. Upon interrupt requests map the interrupt to > GIC. Out of GPIOINT0-122 only 32 can be mapped to GIC SPI, this mapping is > handled by the pinctrl and IRQC driver. > > Cheers, > Prabhakar > > v6->v7: > * Used devm_reset_control_get_exclusive() instead of > devm_reset_control_get_exclusive_by_index() > * Included RB tag from Linus for patch 5/5 > * Switched to newer version of populate_parent_alloc_arg() (patch depends > on https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git/ > patch/?id=178b7e21459e9a7e2a2c369711ef0cc9b1cfbcd7) Please add this patch as part of the series. M. -- Without deviation from the norm, progress is not possible.
Hi Marc, On Wed, Jul 6, 2022 at 8:02 AM Marc Zyngier <maz@kernel.org> wrote: > > On Sun, 03 Jul 2022 20:40:15 +0100, > Lad Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > > Hi All, > > > > The RZ/G2L Interrupt Controller is a front-end for the GIC found on > > Renesas RZ/G2L SoC's with below pins: > > - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI > > interrupts > > - GPIO pins used as external interrupt input pins out of GPIOINT0-122 a > > maximum of only 32 can be mapped to 32 GIC SPI interrupts, > > - NMI edge select. > > > > _____________ > > | GIC | > > | ________ | > > ____________ | | | | > > NMI --------------------------------->| | SPI0-479 | | GIC-600| | > > _______ | |------------>| | | > > | | | | PPI16-31 | | | | > > | | IRQ0-IRQ7 | IRQC |------------>| | | > > P0_P48_4 --->| GPIO |---------------->| | | |________| | > > | |GPIOINT0-122 | | | | > > | |---------------->| TINT0-31 | | | > > |______| |__________| |____________| > > > > The proposed patches add hierarchical IRQ domain, one in IRQC driver and > > another in pinctrl driver. Upon interrupt requests map the interrupt to > > GIC. Out of GPIOINT0-122 only 32 can be mapped to GIC SPI, this mapping is > > handled by the pinctrl and IRQC driver. > > > > Cheers, > > Prabhakar > > > > v6->v7: > > * Used devm_reset_control_get_exclusive() instead of > > devm_reset_control_get_exclusive_by_index() > > * Included RB tag from Linus for patch 5/5 > > * Switched to newer version of populate_parent_alloc_arg() (patch depends > > on https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git/ > > patch/?id=178b7e21459e9a7e2a2c369711ef0cc9b1cfbcd7) > > Please add this patch as part of the series. > Sure will do. Cheers, Prabhakar
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