[v1] Add PLIC support for Renesas RZ/Five SoC

[PATCH 0/2] Add PLIC support for Renesas RZ/Five SoC

Lad Prabhakar posted 2 patches 3 years, 10 months ago

Diff against v1 v2
Download series mbox

There is a newer version of this series

.../sifive,plic-1.0.0.yaml                    | 40 +++++++-
drivers/irqchip/irq-sifive-plic.c             | 95 ++++++++++++++++++-
2 files changed, 127 insertions(+), 8 deletions(-)

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[PATCH 0/2] Add PLIC support for Renesas RZ/Five SoC

Posted by Lad Prabhakar 3 years, 10 months ago

Hi All,

This patch series adds PLIC support for Renesas RZ/Five SoC.

Sending this as an RFC based on the discussion [0].

This patches have been tested with I2C and DMAC interface as these
blocks have EDGE interrupts.

[0] https://lore.kernel.org/linux-arm-kernel/87o80a7t2z.wl-maz@kernel.org/T/

RFC-->v1:
* Fixed review comments pointed by Rob and Geert.
* Changed implementation for EDGE interrupt handling on Renesas RZ/Five SoC.

RFC: https://lore.kernel.org/linux-renesas-soc/
20220524172214.5104-2-prabhakar.mahadev-lad.rj@bp.renesas.com/T/

Cheers,
Prabhakar

Lad Prabhakar (2):
  dt-bindings: interrupt-controller: sifive,plic: Document Renesas
    RZ/Five SoC
  irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

 .../sifive,plic-1.0.0.yaml                    | 40 +++++++-
 drivers/irqchip/irq-sifive-plic.c             | 95 ++++++++++++++++++-
 2 files changed, 127 insertions(+), 8 deletions(-)

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2.25.1