From: Markus Schneider-Pargmann <msp@baylibre.com>
This controller is present on several mediatek hardware. Currently
mt8195 and mt8395 have this controller without a functional difference,
so only one compatible field is added.
The controller can have two forms, as a normal display port and as an
embedded display port.
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
[Bo-Chen: Fix reviewers' comment]
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
---
.../display/mediatek/mediatek,dp.yaml | 101 ++++++++++++++++++
1 file changed, 101 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml
new file mode 100644
index 000000000000..10f50a0dcf49
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Display Port Controller
+
+maintainers:
+ - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+ - Jitao shi <jitao.shi@mediatek.com>
+
+description: |
+ Device tree bindings for the MediaTek display port and
+ embedded display port controller present on some MediaTek SoCs.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8195-dp-tx
+ - mediatek,mt8195-edp-tx
+
+ reg:
+ maxItems: 1
+
+ nvmem-cells:
+ maxItems: 1
+ description: efuse data for display port calibration
+
+ nvmem-cell-names:
+ const: dp_calibration_data
+
+ power-domains:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Input endpoint of the controller, usually dp_intf
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Output endpoint of the controller
+
+ required:
+ - port@0
+ - port@1
+
+ max-lanes:
+ maxItems: 1
+ description: maximum number of lanes supported by the hardware.
+
+ max-linkrate:
+ maxItems: 1
+ description: maximum link rate supported by the hardware and unit is MHz.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - ports
+ - max-lanes
+ - max-linkrate
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/mt8195-power.h>
+ dp_tx@1c600000 {
+ compatible = "mediatek,mt8195-dp-tx";
+ reg = <0x1c600000 0x8000>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
+ interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
+ max-lanes = /bits/ 8 <4>;
+ max-linkrate = /bits/ 16 <8100>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ edp_in: endpoint {
+ remote-endpoint = <&dp_intf0_out>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ edp_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
--
2.18.0On Fri, Jun 10, 2022 at 06:55:13PM +0800, Bo-Chen Chen wrote: > From: Markus Schneider-Pargmann <msp@baylibre.com> > > This controller is present on several mediatek hardware. Currently > mt8195 and mt8395 have this controller without a functional difference, > so only one compatible field is added. > > The controller can have two forms, as a normal display port and as an > embedded display port. > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > [Bo-Chen: Fix reviewers' comment] > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > --- > .../display/mediatek/mediatek,dp.yaml | 101 ++++++++++++++++++ > 1 file changed, 101 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml > new file mode 100644 > index 000000000000..10f50a0dcf49 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml > @@ -0,0 +1,101 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek Display Port Controller > + > +maintainers: > + - Chun-Kuang Hu <chunkuang.hu@kernel.org> > + - Jitao shi <jitao.shi@mediatek.com> > + > +description: | > + Device tree bindings for the MediaTek display port and > + embedded display port controller present on some MediaTek SoCs. > + > +properties: > + compatible: > + enum: > + - mediatek,mt8195-dp-tx > + - mediatek,mt8195-edp-tx > + > + reg: > + maxItems: 1 > + > + nvmem-cells: > + maxItems: 1 > + description: efuse data for display port calibration > + > + nvmem-cell-names: > + const: dp_calibration_data > + > + power-domains: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + description: Input endpoint of the controller, usually dp_intf > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: Output endpoint of the controller > + > + required: > + - port@0 > + - port@1 > + > + max-lanes: > + maxItems: 1 > + description: maximum number of lanes supported by the hardware. We already have a 'data-lanes' property defined in 'video-interfaces.yaml' that can serve this purpose. > + > + max-linkrate: > + maxItems: 1 > + description: maximum link rate supported by the hardware and unit is MHz. Then use '-mhz' suffix on the property name. Then you don't need a type (or maxItems).
On Tue, 2022-06-14 at 14:23 -0600, Rob Herring wrote:
> On Fri, Jun 10, 2022 at 06:55:13PM +0800, Bo-Chen Chen wrote:
> > From: Markus Schneider-Pargmann <msp@baylibre.com>
> >
> > This controller is present on several mediatek hardware. Currently
> > mt8195 and mt8395 have this controller without a functional
> > difference,
> > so only one compatible field is added.
> >
> > The controller can have two forms, as a normal display port and as
> > an
> > embedded display port.
> >
> > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
> > [Bo-Chen: Fix reviewers' comment]
> > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
> > ---
> > .../display/mediatek/mediatek,dp.yaml | 101
> > ++++++++++++++++++
> > 1 file changed, 101 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.ya
> > ml
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.ya
> > ml
> > new file mode 100644
> > index 000000000000..10f50a0dcf49
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.ya
> > ml
> > @@ -0,0 +1,101 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml*__;Iw!!CTRNKA9wMg0ARbw!yqAl1KhfbHqHN7-5aeqhzqeOVhPU_Z5beko5q-y-s5pcfp1WL5oVGvY5UF4EfWm4PWjc5mjBwyBUMsr_RI45ipbhsw$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!yqAl1KhfbHqHN7-5aeqhzqeOVhPU_Z5beko5q-y-s5pcfp1WL5oVGvY5UF4EfWm4PWjc5mjBwyBUMsr_RI5WzYKENQ$
> >
> > +
> > +title: MediaTek Display Port Controller
> > +
> > +maintainers:
> > + - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > + - Jitao shi <jitao.shi@mediatek.com>
> > +
> > +description: |
> > + Device tree bindings for the MediaTek display port and
> > + embedded display port controller present on some MediaTek SoCs.
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - mediatek,mt8195-dp-tx
> > + - mediatek,mt8195-edp-tx
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + nvmem-cells:
> > + maxItems: 1
> > + description: efuse data for display port calibration
> > +
> > + nvmem-cell-names:
> > + const: dp_calibration_data
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + ports:
> > + $ref: /schemas/graph.yaml#/properties/ports
> > + properties:
> > + port@0:
> > + $ref: /schemas/graph.yaml#/properties/port
> > + description: Input endpoint of the controller, usually
> > dp_intf
> > +
> > + port@1:
> > + $ref: /schemas/graph.yaml#/properties/port
> > + description: Output endpoint of the controller
> > +
> > + required:
> > + - port@0
> > + - port@1
> > +
> > + max-lanes:
> > + maxItems: 1
> > + description: maximum number of lanes supported by the
> > hardware.
>
> We already have a 'data-lanes' property defined in
> 'video-interfaces.yaml' that can serve this purpose.
>
Hello Rob,
Thanks for review.
From the description of video-interfaces.yaml, I think it's not quite
match what we need. We only need this value be one of "1,2,4".
Any other suggestion?
> > +
> > + max-linkrate:
> > + maxItems: 1
> > + description: maximum link rate supported by the hardware and
> > unit is MHz.
>
> Then use '-mhz' suffix on the property name. Then you don't need a
> type
> (or maxItems).
OK, I will write like this:
max-linkrate-mhz:
enum: [ 1620, 2700, 5400, 8100 ]
description: maximum link rate supported by the hardware.
BRs,
Bo-Chen
On Thu, Jun 16, 2022 at 09:22:16PM +0800, Rex-BC Chen wrote: > On Tue, 2022-06-14 at 14:23 -0600, Rob Herring wrote: > > On Fri, Jun 10, 2022 at 06:55:13PM +0800, Bo-Chen Chen wrote: > > > From: Markus Schneider-Pargmann <msp@baylibre.com> > > > > > > This controller is present on several mediatek hardware. Currently > > > mt8195 and mt8395 have this controller without a functional > > > difference, > > > so only one compatible field is added. > > > > > > The controller can have two forms, as a normal display port and as > > > an > > > embedded display port. > > > > > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > > > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > > > [Bo-Chen: Fix reviewers' comment] > > > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > > > --- > > > .../display/mediatek/mediatek,dp.yaml | 101 > > > ++++++++++++++++++ > > > 1 file changed, 101 insertions(+) > > > create mode 100644 > > > Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml > > > > > > diff --git > > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.ya > > > ml > > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.ya > > > ml > > > new file mode 100644 > > > index 000000000000..10f50a0dcf49 > > > --- /dev/null > > > +++ > > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.ya > > > ml > > > @@ -0,0 +1,101 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: > > > https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml*__;Iw!!CTRNKA9wMg0ARbw!yqAl1KhfbHqHN7-5aeqhzqeOVhPU_Z5beko5q-y-s5pcfp1WL5oVGvY5UF4EfWm4PWjc5mjBwyBUMsr_RI45ipbhsw$ > > > > > > +$schema: > > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!yqAl1KhfbHqHN7-5aeqhzqeOVhPU_Z5beko5q-y-s5pcfp1WL5oVGvY5UF4EfWm4PWjc5mjBwyBUMsr_RI5WzYKENQ$ > > > > > > + > > > +title: MediaTek Display Port Controller > > > + > > > +maintainers: > > > + - Chun-Kuang Hu <chunkuang.hu@kernel.org> > > > + - Jitao shi <jitao.shi@mediatek.com> > > > + > > > +description: | > > > + Device tree bindings for the MediaTek display port and > > > + embedded display port controller present on some MediaTek SoCs. > > > + > > > +properties: > > > + compatible: > > > + enum: > > > + - mediatek,mt8195-dp-tx > > > + - mediatek,mt8195-edp-tx > > > + > > > + reg: > > > + maxItems: 1 > > > + > > > + nvmem-cells: > > > + maxItems: 1 > > > + description: efuse data for display port calibration > > > + > > > + nvmem-cell-names: > > > + const: dp_calibration_data > > > + > > > + power-domains: > > > + maxItems: 1 > > > + > > > + interrupts: > > > + maxItems: 1 > > > + > > > + ports: > > > + $ref: /schemas/graph.yaml#/properties/ports > > > + properties: > > > + port@0: > > > + $ref: /schemas/graph.yaml#/properties/port > > > + description: Input endpoint of the controller, usually > > > dp_intf > > > + > > > + port@1: > > > + $ref: /schemas/graph.yaml#/properties/port > > > + description: Output endpoint of the controller > > > + > > > + required: > > > + - port@0 > > > + - port@1 > > > + > > > + max-lanes: > > > + maxItems: 1 > > > + description: maximum number of lanes supported by the > > > hardware. > > > > We already have a 'data-lanes' property defined in > > 'video-interfaces.yaml' that can serve this purpose. > > > > Hello Rob, > > Thanks for review. > From the description of video-interfaces.yaml, I think it's not quite > match what we need. We only need this value be one of "1,2,4". data-lanes = <0>; data-lanes = <0 1>; data-lanes = <0 1 2 3>; Limiting the number of lanes to something less than the max is exactly how this property is used in addition to being able to show the mapping of lanes. Rob
On Thu, 2022-06-16 at 15:28 -0600, Rob Herring wrote:
> On Thu, Jun 16, 2022 at 09:22:16PM +0800, Rex-BC Chen wrote:
> > On Tue, 2022-06-14 at 14:23 -0600, Rob Herring wrote:
> > > On Fri, Jun 10, 2022 at 06:55:13PM +0800, Bo-Chen Chen wrote:
> > > > From: Markus Schneider-Pargmann <msp@baylibre.com>
> > > >
> > > > This controller is present on several mediatek hardware.
> > > > Currently
> > > > mt8195 and mt8395 have this controller without a functional
> > > > difference,
> > > > so only one compatible field is added.
> > > >
> > > > The controller can have two forms, as a normal display port and
> > > > as
> > > > an
> > > > embedded display port.
> > > >
> > > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> > > > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
> > > > [Bo-Chen: Fix reviewers' comment]
> > > > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
> > > > ---
> > > > .../display/mediatek/mediatek,dp.yaml | 101
> > > > ++++++++++++++++++
> > > > 1 file changed, 101 insertions(+)
> > > > create mode 100644
> > > > Documentation/devicetree/bindings/display/mediatek/mediatek,dp.
> > > > yaml
> > > >
> > > > diff --git
> > > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,d
> > > > p.ya
> > > > ml
> > > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,d
> > > > p.ya
> > > > ml
> > > > new file mode 100644
> > > > index 000000000000..10f50a0dcf49
> > > > --- /dev/null
> > > > +++
> > > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,d
> > > > p.ya
> > > > ml
> > > > @@ -0,0 +1,101 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > +%YAML 1.2
> > > > +---
> > > > +$id:
> > > >
https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml*__;Iw!!CTRNKA9wMg0ARbw!yqAl1KhfbHqHN7-5aeqhzqeOVhPU_Z5beko5q-y-s5pcfp1WL5oVGvY5UF4EfWm4PWjc5mjBwyBUMsr_RI45ipbhsw$
> > > >
> > > > +$schema:
> > > >
https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!yqAl1KhfbHqHN7-5aeqhzqeOVhPU_Z5beko5q-y-s5pcfp1WL5oVGvY5UF4EfWm4PWjc5mjBwyBUMsr_RI5WzYKENQ$
> > > >
> > > > +
> > > > +title: MediaTek Display Port Controller
> > > > +
> > > > +maintainers:
> > > > + - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > > > + - Jitao shi <jitao.shi@mediatek.com>
> > > > +
> > > > +description: |
> > > > + Device tree bindings for the MediaTek display port and
> > > > + embedded display port controller present on some MediaTek
> > > > SoCs.
> > > > +
> > > > +properties:
> > > > + compatible:
> > > > + enum:
> > > > + - mediatek,mt8195-dp-tx
> > > > + - mediatek,mt8195-edp-tx
> > > > +
> > > > + reg:
> > > > + maxItems: 1
> > > > +
> > > > + nvmem-cells:
> > > > + maxItems: 1
> > > > + description: efuse data for display port calibration
> > > > +
> > > > + nvmem-cell-names:
> > > > + const: dp_calibration_data
> > > > +
> > > > + power-domains:
> > > > + maxItems: 1
> > > > +
> > > > + interrupts:
> > > > + maxItems: 1
> > > > +
> > > > + ports:
> > > > + $ref: /schemas/graph.yaml#/properties/ports
> > > > + properties:
> > > > + port@0:
> > > > + $ref: /schemas/graph.yaml#/properties/port
> > > > + description: Input endpoint of the controller, usually
> > > > dp_intf
> > > > +
> > > > + port@1:
> > > > + $ref: /schemas/graph.yaml#/properties/port
> > > > + description: Output endpoint of the controller
> > > > +
> > > > + required:
> > > > + - port@0
> > > > + - port@1
> > > > +
> > > > + max-lanes:
> > > > + maxItems: 1
> > > > + description: maximum number of lanes supported by the
> > > > hardware.
> > >
> > > We already have a 'data-lanes' property defined in
> > > 'video-interfaces.yaml' that can serve this purpose.
> > >
> >
> > Hello Rob,
> >
> > Thanks for review.
> > From the description of video-interfaces.yaml, I think it's not
> > quite
> > match what we need. We only need this value be one of "1,2,4".
>
> data-lanes = <0>;
> data-lanes = <0 1>;
> data-lanes = <0 1 2 3>;
>
> Limiting the number of lanes to something less than the max is
> exactly
> how this property is used in addition to being able to show the
> mapping
> of lanes.
>
> Rob
Hello Rob,
I modify like this:
data-lanes:
$ref: /schemas/media/video-interfaces.yaml#
description: |
number of lanes supported by the hardware.
The possible values:
1 - For 1 lane enabled in IP.
1 2 - For 2 lanes enabled in IP.
1 2 4 - For 4 lanes enabled in IP.
minItems: 1
maxItems: 3
example:
data-lanes = <1 2 4>;
But I encounter errorr:
Documentation/devicetree/bindings/display/mediatek/mediatek,dp.example.
dtb: dp_tx@1c600000: data-lanes: [[1, 2, 4]] is not of type 'object'
Documentation/devicetree/bindings/display/mediatek/mediatek,dp.example.
dtb: dp_tx@1c600000: data-lanes: [[1, 2, 4]] is not of type 'object'
can you kindly give me some hint for this?
Thanks
BRs,
Bo-Chen
On Fri, 10 Jun 2022 18:55:13 +0800, Bo-Chen Chen wrote: > From: Markus Schneider-Pargmann <msp@baylibre.com> > > This controller is present on several mediatek hardware. Currently > mt8195 and mt8395 have this controller without a functional difference, > so only one compatible field is added. > > The controller can have two forms, as a normal display port and as an > embedded display port. > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > [Bo-Chen: Fix reviewers' comment] > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > --- > .../display/mediatek/mediatek,dp.yaml | 101 ++++++++++++++++++ > 1 file changed, 101 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.example.dtb: dp_tx@1c600000: max-lanes: b'\x04' is not of type 'object', 'array', 'boolean', 'null' From schema: /usr/local/lib/python3.10/dist-packages/dtschema/schemas/dt-core.yaml /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.example.dtb: dp_tx@1c600000: max-linkrate: b'\x1f\xa4' is not of type 'object', 'array', 'boolean', 'null' From schema: /usr/local/lib/python3.10/dist-packages/dtschema/schemas/dt-core.yaml doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/ This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
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