I assume these properties came from a lack of documentation, and the
very reasonable assumption that where there's a clock gate bit in the
CCU, there's a reset bit. But the pin controllers are special and don't
have a module reset line. The only way to reset the pin controller is to
reset the whole VDD_SYS power domain.

This series is preparation for converting the PRCM MFD and legacy clock
drivers to a CCU clock/reset driver like all of the other Allwinner
SoCs. I don't plan to add reset lines that don't actually exist to the
new CCU driver. So we might as well get rid of the references now.
Technically this breaks devicetree compatibility, since the old drivers
expect the reset. But the CCU conversion will be a compatibility break
anyway, so it's a bit of a moot point.


Samuel Holland (3):
  pinctrl: sunxi: Remove reset controller consumers
  ARM: dts: sunxi: Drop resets from r_pio nodes
  dt-bindings: pinctrl: sunxi: Disallow the resets property

 .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml  |  3 ---
 arch/arm/boot/dts/sun6i-a31.dtsi              |  1 -
 arch/arm/boot/dts/sun8i-a23-a33.dtsi          |  1 -
 arch/arm/boot/dts/sun9i-a80.dtsi              |  1 -
 drivers/pinctrl/sunxi/Kconfig                 |  3 ---
 drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c  |  1 -
 drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c   |  1 -
 drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c |  1 -
 drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c   | 22 +---------------
 drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c   | 25 +------------------
 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c  |  1 -
 drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c   |  1 -
 12 files changed, 2 insertions(+), 59 deletions(-)

-- 
2.35.1

On Tue, May 31, 2022 at 7:36 AM Samuel Holland <samuel@sholland.org> wrote:

> I assume these properties came from a lack of documentation, and the
> very reasonable assumption that where there's a clock gate bit in the
> CCU, there's a reset bit. But the pin controllers are special and don't
> have a module reset line. The only way to reset the pin controller is to
> reset the whole VDD_SYS power domain.
>
> This series is preparation for converting the PRCM MFD and legacy clock
> drivers to a CCU clock/reset driver like all of the other Allwinner
> SoCs. I don't plan to add reset lines that don't actually exist to the
> new CCU driver. So we might as well get rid of the references now.
> Technically this breaks devicetree compatibility, since the old drivers
> expect the reset. But the CCU conversion will be a compatibility break
> anyway, so it's a bit of a moot point.
>
>
> Samuel Holland (3):
>   pinctrl: sunxi: Remove reset controller consumers
>   ARM: dts: sunxi: Drop resets from r_pio nodes
>   dt-bindings: pinctrl: sunxi: Disallow the resets property

Patches applied for v5.20!

Yours,
Linus Walleij

Dne torek, 31. maj 2022 ob 07:36:20 CEST je Samuel Holland napisal(a):
> I assume these properties came from a lack of documentation, and the
> very reasonable assumption that where there's a clock gate bit in the
> CCU, there's a reset bit. But the pin controllers are special and don't
> have a module reset line. The only way to reset the pin controller is to
> reset the whole VDD_SYS power domain.
> 
> This series is preparation for converting the PRCM MFD and legacy clock
> drivers to a CCU clock/reset driver like all of the other Allwinner
> SoCs. I don't plan to add reset lines that don't actually exist to the
> new CCU driver. So we might as well get rid of the references now.
> Technically this breaks devicetree compatibility, since the old drivers
> expect the reset. But the CCU conversion will be a compatibility break
> anyway, so it's a bit of a moot point.

If I understand correclty, this would cause only DT forward compatibility 
issue, which happens now and then anyway. Kernel would still be compatible 
with older DTs, it would just ignore that reset, right?

Best regards,
Jernej

> 
> 
> Samuel Holland (3):
>   pinctrl: sunxi: Remove reset controller consumers
>   ARM: dts: sunxi: Drop resets from r_pio nodes
>   dt-bindings: pinctrl: sunxi: Disallow the resets property
> 
>  .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml  |  3 ---
>  arch/arm/boot/dts/sun6i-a31.dtsi              |  1 -
>  arch/arm/boot/dts/sun8i-a23-a33.dtsi          |  1 -
>  arch/arm/boot/dts/sun9i-a80.dtsi              |  1 -
>  drivers/pinctrl/sunxi/Kconfig                 |  3 ---
>  drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c  |  1 -
>  drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c   |  1 -
>  drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c |  1 -
>  drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c   | 22 +---------------
>  drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c   | 25 +------------------
>  drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c  |  1 -
>  drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c   |  1 -
>  12 files changed, 2 insertions(+), 59 deletions(-)
> 
> -- 
> 2.35.1
> 
>

Hi Jernej,

On 5/31/22 10:22 AM, Jernej Škrabec wrote:
> Dne torek, 31. maj 2022 ob 07:36:20 CEST je Samuel Holland napisal(a):
>> I assume these properties came from a lack of documentation, and the
>> very reasonable assumption that where there's a clock gate bit in the
>> CCU, there's a reset bit. But the pin controllers are special and don't
>> have a module reset line. The only way to reset the pin controller is to
>> reset the whole VDD_SYS power domain.
>>
>> This series is preparation for converting the PRCM MFD and legacy clock
>> drivers to a CCU clock/reset driver like all of the other Allwinner
>> SoCs. I don't plan to add reset lines that don't actually exist to the
>> new CCU driver. So we might as well get rid of the references now.
>> Technically this breaks devicetree compatibility, since the old drivers
>> expect the reset. But the CCU conversion will be a compatibility break
>> anyway, so it's a bit of a moot point.
> 
> If I understand correclty, this would cause only DT forward compatibility 
> issue, which happens now and then anyway. Kernel would still be compatible 
> with older DTs, it would just ignore that reset, right?

Right, this only prevents older kernels from working with newer devicetrees. I
brought it up because I'm generally trying to minimize how much we do that.

Regards,
Samuel

Dne sreda, 01. junij 2022 ob 06:42:34 CEST je Samuel Holland napisal(a):
> Hi Jernej,
> 
> On 5/31/22 10:22 AM, Jernej Škrabec wrote:
> > Dne torek, 31. maj 2022 ob 07:36:20 CEST je Samuel Holland napisal(a):
> >> I assume these properties came from a lack of documentation, and the
> >> very reasonable assumption that where there's a clock gate bit in the
> >> CCU, there's a reset bit. But the pin controllers are special and don't
> >> have a module reset line. The only way to reset the pin controller is to
> >> reset the whole VDD_SYS power domain.
> >>
> >> This series is preparation for converting the PRCM MFD and legacy clock
> >> drivers to a CCU clock/reset driver like all of the other Allwinner
> >> SoCs. I don't plan to add reset lines that don't actually exist to the
> >> new CCU driver. So we might as well get rid of the references now.
> >> Technically this breaks devicetree compatibility, since the old drivers
> >> expect the reset. But the CCU conversion will be a compatibility break
> >> anyway, so it's a bit of a moot point.
> > 
> > If I understand correclty, this would cause only DT forward compatibility 
> > issue, which happens now and then anyway. Kernel would still be compatible 
> > with older DTs, it would just ignore that reset, right?
> 
> Right, this only prevents older kernels from working with newer devicetrees. 
I
> brought it up because I'm generally trying to minimize how much we do that.

All good then, this series is:
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej