pinctrl: sunxi: a83t: Fix NAND function name for some pins

[PATCH] pinctrl: sunxi: a83t: Fix NAND function name for some pins

Posted by Samuel Holland 3 years, 11 months ago

The other NAND pins on Port C use the "nand0" function name.
"nand0" also matches all of the other Allwinner SoCs.

Fixes: 4730f33f0d82 ("pinctrl: sunxi: add allwinner A83T PIO controller support")
Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c
index 4ada80317a3b..b5c1a8f363f3 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c
@@ -158,26 +158,26 @@ static const struct sunxi_desc_pin sun8i_a83t_pins[] = {
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
-		  SUNXI_FUNCTION(0x2, "nand"),		/* DQ6 */
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ6 */
 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D6 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
-		  SUNXI_FUNCTION(0x2, "nand"),		/* DQ7 */
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ7 */
 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D7 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
-		  SUNXI_FUNCTION(0x2, "nand"),		/* DQS */
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQS */
 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* RST */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
-		  SUNXI_FUNCTION(0x2, "nand")),		/* CE2 */
+		  SUNXI_FUNCTION(0x2, "nand0")),	/* CE2 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
-		  SUNXI_FUNCTION(0x2, "nand")),		/* CE3 */
+		  SUNXI_FUNCTION(0x2, "nand0")),	/* CE3 */
 	/* Hole */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
-- 
2.35.1

Re: [PATCH] pinctrl: sunxi: a83t: Fix NAND function name for some pins

Posted by Linus Walleij 3 years, 10 months ago

On Thu, May 26, 2022 at 4:49 AM Samuel Holland <samuel@sholland.org> wrote:

> The other NAND pins on Port C use the "nand0" function name.
> "nand0" also matches all of the other Allwinner SoCs.
>
> Fixes: 4730f33f0d82 ("pinctrl: sunxi: add allwinner A83T PIO controller support")
> Signed-off-by: Samuel Holland <samuel@sholland.org>

Patch applied for fixes.

Yours,
Linus Walleij

Re: [PATCH] pinctrl: sunxi: a83t: Fix NAND function name for some pins

Posted by Jernej Škrabec 3 years, 11 months ago

Dne četrtek, 26. maj 2022 ob 04:49:56 CEST je Samuel Holland napisal(a):
> The other NAND pins on Port C use the "nand0" function name.
> "nand0" also matches all of the other Allwinner SoCs.
> 
> Fixes: 4730f33f0d82 ("pinctrl: sunxi: add allwinner A83T PIO controller 
support")
> Signed-off-by: Samuel Holland <samuel@sholland.org>

Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej

> ---
> 
>  drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c b/drivers/pinctrl/
sunxi/pinctrl-sun8i-a83t.c
> index 4ada80317a3b..b5c1a8f363f3 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c
> @@ -158,26 +158,26 @@ static const struct sunxi_desc_pin sun8i_a83t_pins[] = 
{
>  	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
>  		  SUNXI_FUNCTION(0x0, "gpio_in"),
>  		  SUNXI_FUNCTION(0x1, "gpio_out"),
> -		  SUNXI_FUNCTION(0x2, "nand"),		/* DQ6 
*/
> +		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ6 
*/
>  		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D6 
*/
>  	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
>  		  SUNXI_FUNCTION(0x0, "gpio_in"),
>  		  SUNXI_FUNCTION(0x1, "gpio_out"),
> -		  SUNXI_FUNCTION(0x2, "nand"),		/* DQ7 
*/
> +		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ7 
*/
>  		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D7 
*/
>  	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
>  		  SUNXI_FUNCTION(0x0, "gpio_in"),
>  		  SUNXI_FUNCTION(0x1, "gpio_out"),
> -		  SUNXI_FUNCTION(0x2, "nand"),		/* DQS 
*/
> +		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQS 
*/
>  		  SUNXI_FUNCTION(0x3, "mmc2")),		/* RST 
*/
>  	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
>  		  SUNXI_FUNCTION(0x0, "gpio_in"),
>  		  SUNXI_FUNCTION(0x1, "gpio_out"),
> -		  SUNXI_FUNCTION(0x2, "nand")),		/* CE2 
*/
> +		  SUNXI_FUNCTION(0x2, "nand0")),	/* CE2 */
>  	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
>  		  SUNXI_FUNCTION(0x0, "gpio_in"),
>  		  SUNXI_FUNCTION(0x1, "gpio_out"),
> -		  SUNXI_FUNCTION(0x2, "nand")),		/* CE3 
*/
> +		  SUNXI_FUNCTION(0x2, "nand0")),	/* CE3 */
>  	/* Hole */
>  	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
>  		  SUNXI_FUNCTION(0x0, "gpio_in"),
> -- 
> 2.35.1
> 
>