Add YAML schema documentation for PCIe PHY on MediaTek chipsets.
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../bindings/phy/mediatek,pcie-phy.yaml | 75 +++++++++++++++++++
1 file changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
new file mode 100644
index 000000000000..422750cc4121
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek PCIe PHY
+
+maintainers:
+ - Jianjun Wang <jianjun.wang@mediatek.com>
+
+description: |
+ The PCIe PHY supports physical layer functionality for PCIe Gen3 port.
+
+properties:
+ compatible:
+ const: mediatek,mt8195-pcie-phy
+
+ reg:
+ maxItems: 1
+
+ reg-names:
+ items:
+ - const: sif
+
+ "#phy-cells":
+ const: 0
+
+ nvmem-cells:
+ maxItems: 7
+ description:
+ Phandles to nvmem cell that contains the efuse data, if unspecified,
+ default value is used.
+
+ nvmem-cell-names:
+ items:
+ - const: glb_intr
+ - const: tx_ln0_pmos
+ - const: tx_ln0_nmos
+ - const: rx_ln0
+ - const: tx_ln1_pmos
+ - const: tx_ln1_nmos
+ - const: rx_ln1
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ phy@11e80000 {
+ compatible = "mediatek,mt8195-pcie-phy";
+ #phy-cells = <0>;
+ reg = <0x11e80000 0x10000>;
+ reg-names = "sif";
+ nvmem-cells = <&pciephy_glb_intr>,
+ <&pciephy_tx_ln0_pmos>,
+ <&pciephy_tx_ln0_nmos>,
+ <&pciephy_rx_ln0>,
+ <&pciephy_tx_ln1_pmos>,
+ <&pciephy_tx_ln1_nmos>,
+ <&pciephy_rx_ln1>;
+ nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
+ "tx_ln0_nmos", "rx_ln0",
+ "tx_ln1_pmos", "tx_ln1_nmos",
+ "rx_ln1";
+ power-domains = <&spm 2>;
+ };
--
2.18.0
On Fri, 2022-05-20 at 14:49 +0800, Jianjun Wang wrote: > Add YAML schema documentation for PCIe PHY on MediaTek chipsets. > > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> > Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > --- > .../bindings/phy/mediatek,pcie-phy.yaml | 75 > +++++++++++++++++++ > 1 file changed, 75 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/mediatek,pcie- > phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,pcie- > phy.yaml > new file mode 100644 > index 000000000000..422750cc4121 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml > @@ -0,0 +1,75 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek PCIe PHY > + > +maintainers: > + - Jianjun Wang <jianjun.wang@mediatek.com> > + > +description: | > + The PCIe PHY supports physical layer functionality for PCIe Gen3 > port. > + > +properties: > + compatible: > + const: mediatek,mt8195-pcie-phy > + > + reg: > + maxItems: 1 > + > + reg-names: > + items: > + - const: sif > + > + "#phy-cells": > + const: 0 > + > + nvmem-cells: > + maxItems: 7 Seems no need 'maxItems', we can get it from items of 'nvmem-cell- names' > + description: > + Phandles to nvmem cell that contains the efuse data, if > unspecified, > + default value is used. > + > + nvmem-cell-names: > + items: > + - const: glb_intr > + - const: tx_ln0_pmos > + - const: tx_ln0_nmos > + - const: rx_ln0 > + - const: tx_ln1_pmos > + - const: tx_ln1_nmos > + - const: rx_ln1 > + > + power-domains: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - reg-names > + - "#phy-cells" > + > +additionalProperties: false > + > +examples: > + - | > + phy@11e80000 { > + compatible = "mediatek,mt8195-pcie-phy"; > + #phy-cells = <0>; > + reg = <0x11e80000 0x10000>; > + reg-names = "sif"; > + nvmem-cells = <&pciephy_glb_intr>, > + <&pciephy_tx_ln0_pmos>, > + <&pciephy_tx_ln0_nmos>, > + <&pciephy_rx_ln0>, > + <&pciephy_tx_ln1_pmos>, > + <&pciephy_tx_ln1_nmos>, > + <&pciephy_rx_ln1>; > + nvmem-cell-names = "glb_intr", "tx_ln0_pmos", > + "tx_ln0_nmos", "rx_ln0", > + "tx_ln1_pmos", "tx_ln1_nmos", > + "rx_ln1"; > + power-domains = <&spm 2>; > + };
Hi Chunfeng, On Mon, 2022-05-23 at 10:23 +0800, Chunfeng Yun wrote: > On Fri, 2022-05-20 at 14:49 +0800, Jianjun Wang wrote: > > Add YAML schema documentation for PCIe PHY on MediaTek chipsets. > > > > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> > > Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> > > Reviewed-by: AngeloGioacchino Del Regno < > > angelogioacchino.delregno@collabora.com> > > --- > > .../bindings/phy/mediatek,pcie-phy.yaml | 75 > > +++++++++++++++++++ > > 1 file changed, 75 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml > > ...snip... > > + > > + "#phy-cells": > > + const: 0 > > + > > + nvmem-cells: > > + maxItems: 7 > > Seems no need 'maxItems', we can get it from items of 'nvmem-cell- > names' Please see the comment by Krzysztof[1], I guess we need to add this 'maxTems'. [1]: https://lore.kernel.org/lkml/d48c0023-231c-4011-5548-4b260b3fe172@kernel.org/ Thanks. > > > + description: > > + Phandles to nvmem cell that contains the efuse data, if > > unspecified, > > + default value is used. > > + > > + nvmem-cell-names: > > + items: > > + - const: glb_intr > > + - const: tx_ln0_pmos > > + - const: tx_ln0_nmos > > + - const: rx_ln0 > > + - const: tx_ln1_pmos > > + - const: tx_ln1_nmos > > + - const: rx_ln1 > > + > > + power-domains: > > + maxItems: 1 > > + > > +required: > > + - compatible > > + - reg > > + - reg-names > > + - "#phy-cells" > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + phy@11e80000 { > > + compatible = "mediatek,mt8195-pcie-phy"; > > + #phy-cells = <0>; > > + reg = <0x11e80000 0x10000>; > > + reg-names = "sif"; > > + nvmem-cells = <&pciephy_glb_intr>, > > + <&pciephy_tx_ln0_pmos>, > > + <&pciephy_tx_ln0_nmos>, > > + <&pciephy_rx_ln0>, > > + <&pciephy_tx_ln1_pmos>, > > + <&pciephy_tx_ln1_nmos>, > > + <&pciephy_rx_ln1>; > > + nvmem-cell-names = "glb_intr", "tx_ln0_pmos", > > + "tx_ln0_nmos", "rx_ln0", > > + "tx_ln1_pmos", "tx_ln1_nmos", > > + "rx_ln1"; > > + power-domains = <&spm 2>; > > + }; > >
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