Add Performance Monitoring Unit event data for the Arm CPUs listed
below.

Changesets are dependent due to incremental updates to the common events
file and mapfile.csv.

Data is sourced from https://github.com/ARM-software/data

Nick Forrington (20):
  perf vendors events arm64: Arm Cortex-A5
  perf vendors events arm64: Arm Cortex-A7
  perf vendors events arm64: Arm Cortex-A8
  perf vendors events arm64: Arm Cortex-A9
  perf vendors events arm64: Arm Cortex-A15
  perf vendors events arm64: Arm Cortex-A17
  perf vendors events arm64: Arm Cortex-A32
  perf vendors events arm64: Arm Cortex-A34
  perf vendors events arm64: Arm Cortex-A35
  perf vendors events arm64: Arm Cortex-A55
  perf vendors events arm64: Arm Cortex-A510
  perf vendors events arm64: Arm Cortex-A65
  perf vendors events arm64: Arm Cortex-A73
  perf vendors events arm64: Arm Cortex-A75
  perf vendors events arm64: Arm Cortex-A77
  perf vendors events arm64: Arm Cortex-A78
  perf vendors events arm64: Arm Cortex-A710
  perf vendors events arm64: Arm Cortex-X1
  perf vendors events arm64: Arm Cortex-X2
  perf vendors events arm64: Arm Neoverse E1

 .../arch/arm64/arm/cortex-a15/branch.json     |  17 ++
 .../arch/arm64/arm/cortex-a15/bus.json        |  29 +++
 .../arch/arm64/arm/cortex-a15/cache.json      |  80 ++++++
 .../arch/arm64/arm/cortex-a15/exception.json  |   8 +
 .../arm64/arm/cortex-a15/instruction.json     |  59 +++++
 .../arch/arm64/arm/cortex-a15/memory.json     |  20 ++
 .../arch/arm64/arm/cortex-a17/branch.json     |  17 ++
 .../arch/arm64/arm/cortex-a17/bus.json        |  26 ++
 .../arch/arm64/arm/cortex-a17/cache.json      |  53 ++++
 .../arch/arm64/arm/cortex-a17/exception.json  |  11 +
 .../arm64/arm/cortex-a17/instruction.json     |  56 +++++
 .../arch/arm64/arm/cortex-a17/memory.json     |  20 ++
 .../arch/arm64/arm/cortex-a32/branch.json     |  11 +
 .../arch/arm64/arm/cortex-a32/bus.json        |  17 ++
 .../arch/arm64/arm/cortex-a32/cache.json      |  32 +++
 .../arch/arm64/arm/cortex-a32/exception.json  |  14 ++
 .../arm64/arm/cortex-a32/instruction.json     |  29 +++
 .../arch/arm64/arm/cortex-a32/memory.json     |   8 +
 .../arch/arm64/arm/cortex-a34/branch.json     |  11 +
 .../arch/arm64/arm/cortex-a34/bus.json        |  17 ++
 .../arch/arm64/arm/cortex-a34/cache.json      |  32 +++
 .../arch/arm64/arm/cortex-a34/exception.json  |  14 ++
 .../arm64/arm/cortex-a34/instruction.json     |  29 +++
 .../arch/arm64/arm/cortex-a34/memory.json     |   8 +
 .../arch/arm64/arm/cortex-a35/branch.json     |  11 +
 .../arch/arm64/arm/cortex-a35/bus.json        |  17 ++
 .../arch/arm64/arm/cortex-a35/cache.json      |  32 +++
 .../arch/arm64/arm/cortex-a35/exception.json  |  14 ++
 .../arm64/arm/cortex-a35/instruction.json     |  44 ++++
 .../arch/arm64/arm/cortex-a35/memory.json     |   8 +
 .../arch/arm64/arm/cortex-a5/branch.json      |   8 +
 .../arch/arm64/arm/cortex-a5/cache.json       |  23 ++
 .../arch/arm64/arm/cortex-a5/exception.json   |  11 +
 .../arch/arm64/arm/cortex-a5/instruction.json |  29 +++
 .../arch/arm64/arm/cortex-a5/memory.json      |   8 +
 .../arch/arm64/arm/cortex-a510/branch.json    |  59 +++++
 .../arch/arm64/arm/cortex-a510/bus.json       |  17 ++
 .../arch/arm64/arm/cortex-a510/cache.json     | 182 ++++++++++++++
 .../arch/arm64/arm/cortex-a510/exception.json |  14 ++
 .../arm64/arm/cortex-a510/instruction.json    |  95 +++++++
 .../arch/arm64/arm/cortex-a510/memory.json    |  32 +++
 .../arch/arm64/arm/cortex-a510/pipeline.json  | 107 ++++++++
 .../arch/arm64/arm/cortex-a510/pmu.json       |   8 +
 .../arch/arm64/arm/cortex-a510/trace.json     |  32 +++
 .../arch/arm64/arm/cortex-a55/branch.json     |  59 +++++
 .../arch/arm64/arm/cortex-a55/bus.json        |  17 ++
 .../arch/arm64/arm/cortex-a55/cache.json      | 188 ++++++++++++++
 .../arch/arm64/arm/cortex-a55/exception.json  |  20 ++
 .../arm64/arm/cortex-a55/instruction.json     |  65 +++++
 .../arch/arm64/arm/cortex-a55/memory.json     |  17 ++
 .../arch/arm64/arm/cortex-a55/pipeline.json   |  80 ++++++
 .../arch/arm64/arm/cortex-a65/branch.json     |  17 ++
 .../arch/arm64/arm/cortex-a65/bus.json        |  17 ++
 .../arch/arm64/arm/cortex-a65/cache.json      | 236 ++++++++++++++++++
 .../arch/arm64/arm/cortex-a65/dpu.json        |  32 +++
 .../arch/arm64/arm/cortex-a65/exception.json  |  14 ++
 .../arch/arm64/arm/cortex-a65/ifu.json        | 122 +++++++++
 .../arm64/arm/cortex-a65/instruction.json     |  71 ++++++
 .../arch/arm64/arm/cortex-a65/memory.json     |  35 +++
 .../arch/arm64/arm/cortex-a65/pipeline.json   |   8 +
 .../arch/arm64/arm/cortex-a7/branch.json      |   8 +
 .../arch/arm64/arm/cortex-a7/bus.json         |  17 ++
 .../arch/arm64/arm/cortex-a7/cache.json       |  32 +++
 .../arch/arm64/arm/cortex-a7/exception.json   |  11 +
 .../arch/arm64/arm/cortex-a7/instruction.json |  29 +++
 .../arch/arm64/arm/cortex-a7/memory.json      |   8 +
 .../arch/arm64/arm/cortex-a710/branch.json    |  17 ++
 .../arch/arm64/arm/cortex-a710/bus.json       |  20 ++
 .../arch/arm64/arm/cortex-a710/cache.json     | 155 ++++++++++++
 .../arch/arm64/arm/cortex-a710/exception.json |  47 ++++
 .../arm64/arm/cortex-a710/instruction.json    | 134 ++++++++++
 .../arch/arm64/arm/cortex-a710/memory.json    |  41 +++
 .../arch/arm64/arm/cortex-a710/pipeline.json  |  23 ++
 .../arch/arm64/arm/cortex-a710/trace.json     |  29 +++
 .../arch/arm64/arm/cortex-a73/branch.json     |  11 +
 .../arch/arm64/arm/cortex-a73/bus.json        |  23 ++
 .../arch/arm64/arm/cortex-a73/cache.json      | 107 ++++++++
 .../arch/arm64/arm/cortex-a73/etm.json        |  14 ++
 .../arch/arm64/arm/cortex-a73/exception.json  |  14 ++
 .../arm64/arm/cortex-a73/instruction.json     |  65 +++++
 .../arch/arm64/arm/cortex-a73/memory.json     |  14 ++
 .../arch/arm64/arm/cortex-a73/mmu.json        |  44 ++++
 .../arch/arm64/arm/cortex-a73/pipeline.json   |  38 +++
 .../arch/arm64/arm/cortex-a75/branch.json     |  11 +
 .../arch/arm64/arm/cortex-a75/bus.json        |  17 ++
 .../arch/arm64/arm/cortex-a75/cache.json      | 164 ++++++++++++
 .../arch/arm64/arm/cortex-a75/etm.json        |  14 ++
 .../arch/arm64/arm/cortex-a75/exception.json  |  17 ++
 .../arm64/arm/cortex-a75/instruction.json     |  74 ++++++
 .../arch/arm64/arm/cortex-a75/memory.json     |  17 ++
 .../arch/arm64/arm/cortex-a75/mmu.json        |  44 ++++
 .../arch/arm64/arm/cortex-a75/pipeline.json   |  44 ++++
 .../arch/arm64/arm/cortex-a77/branch.json     |  17 ++
 .../arch/arm64/arm/cortex-a77/bus.json        |  17 ++
 .../arch/arm64/arm/cortex-a77/cache.json      | 143 +++++++++++
 .../arch/arm64/arm/cortex-a77/exception.json  |  47 ++++
 .../arm64/arm/cortex-a77/instruction.json     |  77 ++++++
 .../arch/arm64/arm/cortex-a77/memory.json     |  23 ++
 .../arch/arm64/arm/cortex-a77/pipeline.json   |   8 +
 .../arch/arm64/arm/cortex-a78/branch.json     |  17 ++
 .../arch/arm64/arm/cortex-a78/bus.json        |  20 ++
 .../arch/arm64/arm/cortex-a78/cache.json      | 155 ++++++++++++
 .../arch/arm64/arm/cortex-a78/exception.json  |  47 ++++
 .../arm64/arm/cortex-a78/instruction.json     |  80 ++++++
 .../arch/arm64/arm/cortex-a78/memory.json     |  23 ++
 .../arch/arm64/arm/cortex-a78/pipeline.json   |  23 ++
 .../arch/arm64/arm/cortex-a8/branch.json      |   8 +
 .../arch/arm64/arm/cortex-a8/cache.json       |  77 ++++++
 .../arch/arm64/arm/cortex-a8/exception.json   |   5 +
 .../arch/arm64/arm/cortex-a8/instruction.json |  38 +++
 .../arch/arm64/arm/cortex-a8/memory.json      |   5 +
 .../arch/arm64/arm/cortex-a9/branch.json      |   8 +
 .../arch/arm64/arm/cortex-a9/cache.json       |  17 ++
 .../arch/arm64/arm/cortex-a9/exception.json   |   5 +
 .../arch/arm64/arm/cortex-a9/instruction.json |  29 +++
 .../arch/arm64/arm/cortex-a9/memory.json      |   5 +
 .../arch/arm64/arm/cortex-x1/branch.json      |  17 ++
 .../arch/arm64/arm/cortex-x1/bus.json         |  20 ++
 .../arch/arm64/arm/cortex-x1/cache.json       | 155 ++++++++++++
 .../arch/arm64/arm/cortex-x1/exception.json   |  47 ++++
 .../arch/arm64/arm/cortex-x1/instruction.json |  80 ++++++
 .../arch/arm64/arm/cortex-x1/memory.json      |  23 ++
 .../arch/arm64/arm/cortex-x1/pipeline.json    |  23 ++
 .../arch/arm64/arm/cortex-x2/branch.json      |  17 ++
 .../arch/arm64/arm/cortex-x2/bus.json         |  20 ++
 .../arch/arm64/arm/cortex-x2/cache.json       | 155 ++++++++++++
 .../arch/arm64/arm/cortex-x2/exception.json   |  47 ++++
 .../arch/arm64/arm/cortex-x2/instruction.json | 134 ++++++++++
 .../arch/arm64/arm/cortex-x2/memory.json      |  41 +++
 .../arch/arm64/arm/cortex-x2/pipeline.json    |  23 ++
 .../arch/arm64/arm/cortex-x2/trace.json       |  29 +++
 .../arch/arm64/arm/neoverse-e1/branch.json    |  17 ++
 .../arch/arm64/arm/neoverse-e1/bus.json       |  17 ++
 .../arch/arm64/arm/neoverse-e1/cache.json     | 107 ++++++++
 .../arch/arm64/arm/neoverse-e1/exception.json |  14 ++
 .../arm64/arm/neoverse-e1/instruction.json    |  65 +++++
 .../arch/arm64/arm/neoverse-e1/memory.json    |  23 ++
 .../arch/arm64/arm/neoverse-e1/pipeline.json  |   8 +
 .../arch/arm64/arm/neoverse-e1/spe.json       |  14 ++
 .../arch/arm64/common-and-microarch.json      |  66 +++++
 tools/perf/pmu-events/arch/arm64/mapfile.csv  |  20 ++
 141 files changed, 5746 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/branch.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/bus.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/cache.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/exception.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/instruction.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/memory.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/branch.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/bus.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/cache.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/exception.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/instruction.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/memory.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/branch.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/bus.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/cache.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/exception.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/instruction.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/memory.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/branch.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/bus.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/cache.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/exception.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/instruction.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/memory.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/branch.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/bus.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/cache.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/exception.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/instruction.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/memory.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a5/branch.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a5/cache.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a5/exception.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a5/instruction.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a5/memory.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/branch.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/bus.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/cache.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/exception.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/instruction.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/memory.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/pipeline.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/pmu.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/trace.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/branch.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/bus.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/cache.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/exception.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/instruction.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/memory.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/pipeline.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/branch.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/bus.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/cache.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/dpu.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/exception.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/ifu.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/instruction.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/memory.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/pipeline.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/branch.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/bus.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/cache.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/exception.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/instruction.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/memory.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/branch.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/bus.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/cache.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/exception.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/instruction.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/memory.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/pipeline.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/trace.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/branch.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/bus.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/cache.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/etm.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/exception.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/instruction.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/memory.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/mmu.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/pipeline.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/branch.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/bus.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/cache.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/etm.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/exception.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/instruction.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/memory.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/mmu.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/pipeline.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/branch.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/bus.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/cache.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/exception.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/instruction.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/memory.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/pipeline.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/branch.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/bus.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/cache.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/exception.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/instruction.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/memory.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/pipeline.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/branch.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/cache.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/exception.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/instruction.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/memory.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/branch.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/cache.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/exception.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/instruction.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/memory.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/branch.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/bus.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/cache.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/exception.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/instruction.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/memory.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/pipeline.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/branch.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/bus.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/cache.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/exception.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/instruction.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/memory.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/pipeline.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/trace.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/branch.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/bus.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/cache.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/exception.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/instruction.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/memory.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/pipeline.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/spe.json

-- 
2.25.1

Em Tue, May 10, 2022 at 11:47:38AM +0100, Nick Forrington escreveu:
> Add Performance Monitoring Unit event data for the Arm CPUs listed
> below.
> 
> Changesets are dependent due to incremental updates to the common events
> file and mapfile.csv.
> 
> Data is sourced from https://github.com/ARM-software/data

Waiting for reviews to merge this.

- Arnaldo
 
> Nick Forrington (20):
>   perf vendors events arm64: Arm Cortex-A5
>   perf vendors events arm64: Arm Cortex-A7
>   perf vendors events arm64: Arm Cortex-A8
>   perf vendors events arm64: Arm Cortex-A9
>   perf vendors events arm64: Arm Cortex-A15
>   perf vendors events arm64: Arm Cortex-A17
>   perf vendors events arm64: Arm Cortex-A32
>   perf vendors events arm64: Arm Cortex-A34
>   perf vendors events arm64: Arm Cortex-A35
>   perf vendors events arm64: Arm Cortex-A55
>   perf vendors events arm64: Arm Cortex-A510
>   perf vendors events arm64: Arm Cortex-A65
>   perf vendors events arm64: Arm Cortex-A73
>   perf vendors events arm64: Arm Cortex-A75
>   perf vendors events arm64: Arm Cortex-A77
>   perf vendors events arm64: Arm Cortex-A78
>   perf vendors events arm64: Arm Cortex-A710
>   perf vendors events arm64: Arm Cortex-X1
>   perf vendors events arm64: Arm Cortex-X2
>   perf vendors events arm64: Arm Neoverse E1
> 
>  .../arch/arm64/arm/cortex-a15/branch.json     |  17 ++
>  .../arch/arm64/arm/cortex-a15/bus.json        |  29 +++
>  .../arch/arm64/arm/cortex-a15/cache.json      |  80 ++++++
>  .../arch/arm64/arm/cortex-a15/exception.json  |   8 +
>  .../arm64/arm/cortex-a15/instruction.json     |  59 +++++
>  .../arch/arm64/arm/cortex-a15/memory.json     |  20 ++
>  .../arch/arm64/arm/cortex-a17/branch.json     |  17 ++
>  .../arch/arm64/arm/cortex-a17/bus.json        |  26 ++
>  .../arch/arm64/arm/cortex-a17/cache.json      |  53 ++++
>  .../arch/arm64/arm/cortex-a17/exception.json  |  11 +
>  .../arm64/arm/cortex-a17/instruction.json     |  56 +++++
>  .../arch/arm64/arm/cortex-a17/memory.json     |  20 ++
>  .../arch/arm64/arm/cortex-a32/branch.json     |  11 +
>  .../arch/arm64/arm/cortex-a32/bus.json        |  17 ++
>  .../arch/arm64/arm/cortex-a32/cache.json      |  32 +++
>  .../arch/arm64/arm/cortex-a32/exception.json  |  14 ++
>  .../arm64/arm/cortex-a32/instruction.json     |  29 +++
>  .../arch/arm64/arm/cortex-a32/memory.json     |   8 +
>  .../arch/arm64/arm/cortex-a34/branch.json     |  11 +
>  .../arch/arm64/arm/cortex-a34/bus.json        |  17 ++
>  .../arch/arm64/arm/cortex-a34/cache.json      |  32 +++
>  .../arch/arm64/arm/cortex-a34/exception.json  |  14 ++
>  .../arm64/arm/cortex-a34/instruction.json     |  29 +++
>  .../arch/arm64/arm/cortex-a34/memory.json     |   8 +
>  .../arch/arm64/arm/cortex-a35/branch.json     |  11 +
>  .../arch/arm64/arm/cortex-a35/bus.json        |  17 ++
>  .../arch/arm64/arm/cortex-a35/cache.json      |  32 +++
>  .../arch/arm64/arm/cortex-a35/exception.json  |  14 ++
>  .../arm64/arm/cortex-a35/instruction.json     |  44 ++++
>  .../arch/arm64/arm/cortex-a35/memory.json     |   8 +
>  .../arch/arm64/arm/cortex-a5/branch.json      |   8 +
>  .../arch/arm64/arm/cortex-a5/cache.json       |  23 ++
>  .../arch/arm64/arm/cortex-a5/exception.json   |  11 +
>  .../arch/arm64/arm/cortex-a5/instruction.json |  29 +++
>  .../arch/arm64/arm/cortex-a5/memory.json      |   8 +
>  .../arch/arm64/arm/cortex-a510/branch.json    |  59 +++++
>  .../arch/arm64/arm/cortex-a510/bus.json       |  17 ++
>  .../arch/arm64/arm/cortex-a510/cache.json     | 182 ++++++++++++++
>  .../arch/arm64/arm/cortex-a510/exception.json |  14 ++
>  .../arm64/arm/cortex-a510/instruction.json    |  95 +++++++
>  .../arch/arm64/arm/cortex-a510/memory.json    |  32 +++
>  .../arch/arm64/arm/cortex-a510/pipeline.json  | 107 ++++++++
>  .../arch/arm64/arm/cortex-a510/pmu.json       |   8 +
>  .../arch/arm64/arm/cortex-a510/trace.json     |  32 +++
>  .../arch/arm64/arm/cortex-a55/branch.json     |  59 +++++
>  .../arch/arm64/arm/cortex-a55/bus.json        |  17 ++
>  .../arch/arm64/arm/cortex-a55/cache.json      | 188 ++++++++++++++
>  .../arch/arm64/arm/cortex-a55/exception.json  |  20 ++
>  .../arm64/arm/cortex-a55/instruction.json     |  65 +++++
>  .../arch/arm64/arm/cortex-a55/memory.json     |  17 ++
>  .../arch/arm64/arm/cortex-a55/pipeline.json   |  80 ++++++
>  .../arch/arm64/arm/cortex-a65/branch.json     |  17 ++
>  .../arch/arm64/arm/cortex-a65/bus.json        |  17 ++
>  .../arch/arm64/arm/cortex-a65/cache.json      | 236 ++++++++++++++++++
>  .../arch/arm64/arm/cortex-a65/dpu.json        |  32 +++
>  .../arch/arm64/arm/cortex-a65/exception.json  |  14 ++
>  .../arch/arm64/arm/cortex-a65/ifu.json        | 122 +++++++++
>  .../arm64/arm/cortex-a65/instruction.json     |  71 ++++++
>  .../arch/arm64/arm/cortex-a65/memory.json     |  35 +++
>  .../arch/arm64/arm/cortex-a65/pipeline.json   |   8 +
>  .../arch/arm64/arm/cortex-a7/branch.json      |   8 +
>  .../arch/arm64/arm/cortex-a7/bus.json         |  17 ++
>  .../arch/arm64/arm/cortex-a7/cache.json       |  32 +++
>  .../arch/arm64/arm/cortex-a7/exception.json   |  11 +
>  .../arch/arm64/arm/cortex-a7/instruction.json |  29 +++
>  .../arch/arm64/arm/cortex-a7/memory.json      |   8 +
>  .../arch/arm64/arm/cortex-a710/branch.json    |  17 ++
>  .../arch/arm64/arm/cortex-a710/bus.json       |  20 ++
>  .../arch/arm64/arm/cortex-a710/cache.json     | 155 ++++++++++++
>  .../arch/arm64/arm/cortex-a710/exception.json |  47 ++++
>  .../arm64/arm/cortex-a710/instruction.json    | 134 ++++++++++
>  .../arch/arm64/arm/cortex-a710/memory.json    |  41 +++
>  .../arch/arm64/arm/cortex-a710/pipeline.json  |  23 ++
>  .../arch/arm64/arm/cortex-a710/trace.json     |  29 +++
>  .../arch/arm64/arm/cortex-a73/branch.json     |  11 +
>  .../arch/arm64/arm/cortex-a73/bus.json        |  23 ++
>  .../arch/arm64/arm/cortex-a73/cache.json      | 107 ++++++++
>  .../arch/arm64/arm/cortex-a73/etm.json        |  14 ++
>  .../arch/arm64/arm/cortex-a73/exception.json  |  14 ++
>  .../arm64/arm/cortex-a73/instruction.json     |  65 +++++
>  .../arch/arm64/arm/cortex-a73/memory.json     |  14 ++
>  .../arch/arm64/arm/cortex-a73/mmu.json        |  44 ++++
>  .../arch/arm64/arm/cortex-a73/pipeline.json   |  38 +++
>  .../arch/arm64/arm/cortex-a75/branch.json     |  11 +
>  .../arch/arm64/arm/cortex-a75/bus.json        |  17 ++
>  .../arch/arm64/arm/cortex-a75/cache.json      | 164 ++++++++++++
>  .../arch/arm64/arm/cortex-a75/etm.json        |  14 ++
>  .../arch/arm64/arm/cortex-a75/exception.json  |  17 ++
>  .../arm64/arm/cortex-a75/instruction.json     |  74 ++++++
>  .../arch/arm64/arm/cortex-a75/memory.json     |  17 ++
>  .../arch/arm64/arm/cortex-a75/mmu.json        |  44 ++++
>  .../arch/arm64/arm/cortex-a75/pipeline.json   |  44 ++++
>  .../arch/arm64/arm/cortex-a77/branch.json     |  17 ++
>  .../arch/arm64/arm/cortex-a77/bus.json        |  17 ++
>  .../arch/arm64/arm/cortex-a77/cache.json      | 143 +++++++++++
>  .../arch/arm64/arm/cortex-a77/exception.json  |  47 ++++
>  .../arm64/arm/cortex-a77/instruction.json     |  77 ++++++
>  .../arch/arm64/arm/cortex-a77/memory.json     |  23 ++
>  .../arch/arm64/arm/cortex-a77/pipeline.json   |   8 +
>  .../arch/arm64/arm/cortex-a78/branch.json     |  17 ++
>  .../arch/arm64/arm/cortex-a78/bus.json        |  20 ++
>  .../arch/arm64/arm/cortex-a78/cache.json      | 155 ++++++++++++
>  .../arch/arm64/arm/cortex-a78/exception.json  |  47 ++++
>  .../arm64/arm/cortex-a78/instruction.json     |  80 ++++++
>  .../arch/arm64/arm/cortex-a78/memory.json     |  23 ++
>  .../arch/arm64/arm/cortex-a78/pipeline.json   |  23 ++
>  .../arch/arm64/arm/cortex-a8/branch.json      |   8 +
>  .../arch/arm64/arm/cortex-a8/cache.json       |  77 ++++++
>  .../arch/arm64/arm/cortex-a8/exception.json   |   5 +
>  .../arch/arm64/arm/cortex-a8/instruction.json |  38 +++
>  .../arch/arm64/arm/cortex-a8/memory.json      |   5 +
>  .../arch/arm64/arm/cortex-a9/branch.json      |   8 +
>  .../arch/arm64/arm/cortex-a9/cache.json       |  17 ++
>  .../arch/arm64/arm/cortex-a9/exception.json   |   5 +
>  .../arch/arm64/arm/cortex-a9/instruction.json |  29 +++
>  .../arch/arm64/arm/cortex-a9/memory.json      |   5 +
>  .../arch/arm64/arm/cortex-x1/branch.json      |  17 ++
>  .../arch/arm64/arm/cortex-x1/bus.json         |  20 ++
>  .../arch/arm64/arm/cortex-x1/cache.json       | 155 ++++++++++++
>  .../arch/arm64/arm/cortex-x1/exception.json   |  47 ++++
>  .../arch/arm64/arm/cortex-x1/instruction.json |  80 ++++++
>  .../arch/arm64/arm/cortex-x1/memory.json      |  23 ++
>  .../arch/arm64/arm/cortex-x1/pipeline.json    |  23 ++
>  .../arch/arm64/arm/cortex-x2/branch.json      |  17 ++
>  .../arch/arm64/arm/cortex-x2/bus.json         |  20 ++
>  .../arch/arm64/arm/cortex-x2/cache.json       | 155 ++++++++++++
>  .../arch/arm64/arm/cortex-x2/exception.json   |  47 ++++
>  .../arch/arm64/arm/cortex-x2/instruction.json | 134 ++++++++++
>  .../arch/arm64/arm/cortex-x2/memory.json      |  41 +++
>  .../arch/arm64/arm/cortex-x2/pipeline.json    |  23 ++
>  .../arch/arm64/arm/cortex-x2/trace.json       |  29 +++
>  .../arch/arm64/arm/neoverse-e1/branch.json    |  17 ++
>  .../arch/arm64/arm/neoverse-e1/bus.json       |  17 ++
>  .../arch/arm64/arm/neoverse-e1/cache.json     | 107 ++++++++
>  .../arch/arm64/arm/neoverse-e1/exception.json |  14 ++
>  .../arm64/arm/neoverse-e1/instruction.json    |  65 +++++
>  .../arch/arm64/arm/neoverse-e1/memory.json    |  23 ++
>  .../arch/arm64/arm/neoverse-e1/pipeline.json  |   8 +
>  .../arch/arm64/arm/neoverse-e1/spe.json       |  14 ++
>  .../arch/arm64/common-and-microarch.json      |  66 +++++
>  tools/perf/pmu-events/arch/arm64/mapfile.csv  |  20 ++
>  141 files changed, 5746 insertions(+)
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/branch.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/bus.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/cache.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/exception.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/instruction.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/memory.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/branch.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/bus.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/cache.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/exception.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/instruction.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/memory.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/branch.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/bus.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/cache.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/exception.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/instruction.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/memory.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/branch.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/bus.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/cache.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/exception.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/instruction.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/memory.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/branch.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/bus.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/cache.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/exception.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/instruction.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/memory.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a5/branch.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a5/cache.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a5/exception.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a5/instruction.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a5/memory.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/branch.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/bus.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/cache.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/exception.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/instruction.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/memory.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/pipeline.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/pmu.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/trace.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/branch.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/bus.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/cache.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/exception.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/instruction.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/memory.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/pipeline.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/branch.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/bus.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/cache.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/dpu.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/exception.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/ifu.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/instruction.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/memory.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/pipeline.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/branch.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/bus.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/cache.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/exception.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/instruction.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/memory.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/branch.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/bus.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/cache.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/exception.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/instruction.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/memory.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/pipeline.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/trace.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/branch.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/bus.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/cache.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/etm.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/exception.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/instruction.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/memory.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/mmu.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/pipeline.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/branch.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/bus.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/cache.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/etm.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/exception.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/instruction.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/memory.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/mmu.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/pipeline.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/branch.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/bus.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/cache.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/exception.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/instruction.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/memory.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/pipeline.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/branch.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/bus.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/cache.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/exception.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/instruction.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/memory.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/pipeline.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/branch.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/cache.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/exception.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/instruction.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/memory.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/branch.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/cache.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/exception.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/instruction.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/memory.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/branch.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/bus.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/cache.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/exception.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/instruction.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/memory.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/pipeline.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/branch.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/bus.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/cache.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/exception.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/instruction.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/memory.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/pipeline.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/trace.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/branch.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/bus.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/cache.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/exception.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/instruction.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/memory.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/pipeline.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/spe.json
> 
> -- 
> 2.25.1

-- 

- Arnaldo

On 10/05/2022 16:50, Arnaldo Carvalho de Melo wrote:
> Em Tue, May 10, 2022 at 11:47:38AM +0100, Nick Forrington escreveu:
>> Add Performance Monitoring Unit event data for the Arm CPUs listed
>> below.
>>
>> Changesets are dependent due to incremental updates to the common events
>> file and mapfile.csv.
>>
>> Data is sourced fromhttps://github.com/ARM-software/data
> Waiting for reviews to merge this.
> 

I'll have a closer look this week.

@Nick, Just curious, do you have some tool/script to convert from the 
JSON format @ https://github.com/ARM-software/data/blob/master/pmu/ to 
the "linux" format?

Thanks,
John

On 10/05/2022 16:55, John Garry wrote:
> On 10/05/2022 16:50, Arnaldo Carvalho de Melo wrote:
>> Em Tue, May 10, 2022 at 11:47:38AM +0100, Nick Forrington escreveu:
>>> Add Performance Monitoring Unit event data for the Arm CPUs listed
>>> below.
>>>
>>> Changesets are dependent due to incremental updates to the common 
>>> events
>>> file and mapfile.csv.
>>>
>>> Data is sourced fromhttps://github.com/ARM-software/data
>> Waiting for reviews to merge this.
>>
>
> I'll have a closer look this week.
>
> @Nick, Just curious, do you have some tool/script to convert from the 
> JSON format @ https://github.com/ARM-software/data/blob/master/pmu/ to 
> the "linux" format?

Thanks John.

We do have a conversion script, although it isn't publically available 
anywhere at the moment.

Thanks,
Nick

On 12/05/2022 14:01, Nick Forrington wrote:
> On 10/05/2022 16:55, John Garry wrote:
>> On 10/05/2022 16:50, Arnaldo Carvalho de Melo wrote:
>>> Em Tue, May 10, 2022 at 11:47:38AM +0100, Nick Forrington escreveu:
>>>> Add Performance Monitoring Unit event data for the Arm CPUs listed
>>>> below.
>>>>
>>>> Changesets are dependent due to incremental updates to the common 
>>>> events
>>>> file and mapfile.csv.
>>>>
>>>> Data is sourced fromhttps://github.com/ARM-software/data
>>> Waiting for reviews to merge this.
>>>
>>
>> I'll have a closer look this week

Generally this looks ok:

Reviewed-by: John Garry <john.garry@huawei.com>

If you are feeling particularly helpful then you can add support for any 
events missing to pre-existing core support, like a57-a72.

Thanks,
john

On 12/05/2022 16:52, John Garry wrote:
> Generally this looks ok:
>
> Reviewed-by: John Garry <john.garry@huawei.com>
>
> If you are feeling particularly helpful then you can add support for 
> any events missing to pre-existing core support, like a57-a72.

Thanks John.

I'll submit a separate patch for A57/A72.

Nick

On Thu, May 12, 2022 at 8:53 AM John Garry <john.garry@huawei.com> wrote:
>
> On 12/05/2022 14:01, Nick Forrington wrote:
> > On 10/05/2022 16:55, John Garry wrote:
> >> On 10/05/2022 16:50, Arnaldo Carvalho de Melo wrote:
> >>> Em Tue, May 10, 2022 at 11:47:38AM +0100, Nick Forrington escreveu:
> >>>> Add Performance Monitoring Unit event data for the Arm CPUs listed
> >>>> below.
> >>>>
> >>>> Changesets are dependent due to incremental updates to the common
> >>>> events
> >>>> file and mapfile.csv.
> >>>>
> >>>> Data is sourced fromhttps://github.com/ARM-software/data
> >>> Waiting for reviews to merge this.
> >>>
> >>
> >> I'll have a closer look this week
>
> Generally this looks ok:
>
> Reviewed-by: John Garry <john.garry@huawei.com>
>
> If you are feeling particularly helpful then you can add support for any
> events missing to pre-existing core support, like a57-a72.
>
> Thanks,
> john

I'll raise John's "ok" and say this looks great! :-D Some thoughts:

The mapfile.csv cpuid values don't directly align with:
https://github.com/ARM-software/data/blob/master/cpus.json
but this definitely looks deliberate.

The new events lack the PMU "Unit" value. The current perf json is
pretty free form and leads to problems if two PMUs are present.
Context is here:
https://lore.kernel.org/lkml/CAP-5=fWRRZsyJZ-gky-FOFz79zW_3r78d_0APpj5sf66HqTpLw@mail.gmail.com/

My idea to rationalize this is to mirror what is already done in
sysfs, that is the event data is specific to a PMU. As a lot of "Unit"
values are missing from events on x86 a reasonable guess if the "Unit"
is missing is to use "cpu". Poking a Google Pixel 4a, I see that all
PMU data is in "armv8_pmuv3". So for ARM I could guess this is always
the case, ie all events should belong to armv8_pmuv3. This may not be
right and could lead to confusion like an event BR_COND_MIS_PRED
having an alias of "armv8_pmuv3/BR_COND_MIS_PRED/" but it really
should have some other PMU name in there. I just raise this in case
there is a fix for this we could incorporate into this patch series,
maybe "armv8_pmuv3" is always the PMU and my life is easy.

Thanks,
Ian

On 15/05/2022 23:03, Ian Rogers wrote:
> On Thu, May 12, 2022 at 8:53 AM John Garry <john.garry@huawei.com> wrote:
>
> Generally this looks ok:
>
> Reviewed-by: John Garry <john.garry@huawei.com>
>
> If you are feeling particularly helpful then you can add support for any
> events missing to pre-existing core support, like a57-a72.
>
> I'll raise John's "ok" and say this looks great! :-D Some thoughts:

Thanks Ian!

> The mapfile.csv cpuid values don't directly align with:
> https://github.com/ARM-software/data/blob/master/cpus.json
> but this definitely looks deliberate.

Correct - they use different formats.

mapfile.csv uses the MIDR format

https://developer.arm.com/documentation/100442/0100/register-descriptions/aarch64-system-registers/midr-el1--main-id-register--el1

The cpus.json "cpuid" is the implementer and part number from the MIDR 
(the other fields are always fixed in mapfile.csv)
> The new events lack the PMU "Unit" value. The current perf json is
> pretty free form and leads to problems if two PMUs are present.
> Context is here:
> https://lore.kernel.org/lkml/CAP-5=fWRRZsyJZ-gky-FOFz79zW_3r78d_0APpj5sf66HqTpLw@mail.gmail.com/
>
> My idea to rationalize this is to mirror what is already done in
> sysfs, that is the event data is specific to a PMU. As a lot of "Unit"
> values are missing from events on x86 a reasonable guess if the "Unit"
> is missing is to use "cpu". Poking a Google Pixel 4a, I see that all
> PMU data is in "armv8_pmuv3". So for ARM I could guess this is always
> the case, ie all events should belong to armv8_pmuv3. This may not be
> right and could lead to confusion like an event BR_COND_MIS_PRED
> having an alias of "armv8_pmuv3/BR_COND_MIS_PRED/" but it really
> should have some other PMU name in there. I just raise this in case
> there is a fix for this we could incorporate into this patch series,
> maybe "armv8_pmuv3" is always the PMU and my life is easy.

My understanding is that all JSON events under arm64/arm apply to the 
CPU PMU, although there could be 2 (or more) armv8_pmuv3 devices in a 
herterogeneous system (armv8_pmuv3_0, armv8_pmuv3_1, ...) - each with 
different events.

So I don't think static "Unit" data would be helpful, but it should be 
possible to map JSON events to appropriate CPUs with existing data.

e.g. /sys/bus/event_source/devices/armv8_pmuv3_0/cpus shows the CPUs 
associated with a PMU device, and each CPU can be mapped to JSON events 
via the MIDR (as is done already)

Thanks,
Nick

On 15/05/2022 23:03, Ian Rogers wrote:
> I'll raise John's "ok" and say this looks great!:-D  Some thoughts:
> 
> The mapfile.csv cpuid values don't directly align with:
> https://github.com/ARM-software/data/blob/master/cpus.json
> but this definitely looks deliberate.
> 

Hi Ian,

> The new events lack the PMU "Unit" value.

For arm support we work on the basis that no "Unit" means CPU PMU. I 
assume the same for other archs, but maybe this hybrid PMU support 
changes that.

> The current perf json is
> pretty free form and leads to problems if two PMUs are present.

Can you clarify - for my benefit - exactly what you mean by "two PMUs 
are present"?

> Context is here:
> https://lore.kernel.org/lkml/CAP-5=fWRRZsyJZ-gky-FOFz79zW_3r78d_0APpj5sf66HqTpLw@mail.gmail.com/
> 

We have another problem but I am not sure if exactly the same.

The issue is that if we have an event alias "cycles" for an uncore PMU, 
then if we use "stat" command then perf tool matches "cycles" to CPU 
cycles and not the uncore PMU, which we would not want.

We have ways to work around it, though.

> My idea to rationalize this is to mirror what is already done in
> sysfs, that is the event data is specific to a PMU. As a lot of "Unit"
> values are missing from events on x86 a reasonable guess if the "Unit"
> is missing is to use "cpu". 

This sounds like what I mentioned in the reply to 1/20:

"I had a patch series which makes perf read the armv8 pmu
sysfs event file to learn all the events which the core supports and
create the aliases from that. So, in this, we don't require the JSONs to
list these events explicitly. "

Is this like what Andi was talking about in terms of runtime loading?

> Poking a Google Pixel 4a, I see that all
> PMU data is in "armv8_pmuv3". So for ARM I could guess this is always
> the case, ie all events should belong to armv8_pmuv3. This may not be
> right and could lead to confusion like an event BR_COND_MIS_PRED
> having an alias of "armv8_pmuv3/BR_COND_MIS_PRED/" but it really
> should have some other PMU name in there. I just raise this in case
> there is a fix for this we could incorporate into this patch series,
> maybe "armv8_pmuv3" is always the PMU and my life is easy.

Thanks,
John

On Mon, May 16, 2022 at 4:10 AM John Garry <john.garry@huawei.com> wrote:
>
> On 15/05/2022 23:03, Ian Rogers wrote:
> > I'll raise John's "ok" and say this looks great!:-D  Some thoughts:
> >
> > The mapfile.csv cpuid values don't directly align with:
> > https://github.com/ARM-software/data/blob/master/cpus.json
> > but this definitely looks deliberate.
> >
>
> Hi Ian,
>
> > The new events lack the PMU "Unit" value.
>
> For arm support we work on the basis that no "Unit" means CPU PMU. I
> assume the same for other archs, but maybe this hybrid PMU support
> changes that.
>
> > The current perf json is
> > pretty free form and leads to problems if two PMUs are present.
>
> Can you clarify - for my benefit - exactly what you mean by "two PMUs
> are present"?

On Alderlake there is a cpu_core and cpu_atom. The event codes, etc.
vary between them - there is no notion of architecture standard
events.

> > Context is here:
> > https://lore.kernel.org/lkml/CAP-5=fWRRZsyJZ-gky-FOFz79zW_3r78d_0APpj5sf66HqTpLw@mail.gmail.com/
> >
>
> We have another problem but I am not sure if exactly the same.
>
> The issue is that if we have an event alias "cycles" for an uncore PMU,
> then if we use "stat" command then perf tool matches "cycles" to CPU
> cycles and not the uncore PMU, which we would not want.
>
> We have ways to work around it, though.

Ack.

> > My idea to rationalize this is to mirror what is already done in
> > sysfs, that is the event data is specific to a PMU. As a lot of "Unit"
> > values are missing from events on x86 a reasonable guess if the "Unit"
> > is missing is to use "cpu".
>
> This sounds like what I mentioned in the reply to 1/20:
>
> "I had a patch series which makes perf read the armv8 pmu
> sysfs event file to learn all the events which the core supports and
> create the aliases from that. So, in this, we don't require the JSONs to
> list these events explicitly. "
>
> Is this like what Andi was talking about in terms of runtime loading?

I think Andi is talking about loading the json style events at
runtime. The existing jevents.c code could be linked into the perf
tool whereas the jevents.py rewrite would be harder.

Thanks,
Ian

> > Poking a Google Pixel 4a, I see that all
> > PMU data is in "armv8_pmuv3". So for ARM I could guess this is always
> > the case, ie all events should belong to armv8_pmuv3. This may not be
> > right and could lead to confusion like an event BR_COND_MIS_PRED
> > having an alias of "armv8_pmuv3/BR_COND_MIS_PRED/" but it really
> > should have some other PMU name in there. I just raise this in case
> > there is a fix for this we could incorporate into this patch series,
> > maybe "armv8_pmuv3" is always the PMU and my life is easy.
>
> Thanks,
> John

Hi Nick,

On 2022-05-10 11:47, Nick Forrington wrote:
> Add Performance Monitoring Unit event data for the Arm CPUs listed
> below.
> 
> Changesets are dependent due to incremental updates to the common events
> file and mapfile.csv.
> 
> Data is sourced from https://github.com/ARM-software/data
> 
> Nick Forrington (20):
>    perf vendors events arm64: Arm Cortex-A5
>    perf vendors events arm64: Arm Cortex-A7
>    perf vendors events arm64: Arm Cortex-A8
>    perf vendors events arm64: Arm Cortex-A9
>    perf vendors events arm64: Arm Cortex-A15
>    perf vendors events arm64: Arm Cortex-A17
>    perf vendors events arm64: Arm Cortex-A32

Obligatory question over anything relating to the above CPUs being in an 
"arch/arm64" directory... ;)

Cheers,
Robin.

>    perf vendors events arm64: Arm Cortex-A34
>    perf vendors events arm64: Arm Cortex-A35
>    perf vendors events arm64: Arm Cortex-A55
>    perf vendors events arm64: Arm Cortex-A510
>    perf vendors events arm64: Arm Cortex-A65
>    perf vendors events arm64: Arm Cortex-A73
>    perf vendors events arm64: Arm Cortex-A75
>    perf vendors events arm64: Arm Cortex-A77
>    perf vendors events arm64: Arm Cortex-A78
>    perf vendors events arm64: Arm Cortex-A710
>    perf vendors events arm64: Arm Cortex-X1
>    perf vendors events arm64: Arm Cortex-X2
>    perf vendors events arm64: Arm Neoverse E1
> 
>   .../arch/arm64/arm/cortex-a15/branch.json     |  17 ++
>   .../arch/arm64/arm/cortex-a15/bus.json        |  29 +++
>   .../arch/arm64/arm/cortex-a15/cache.json      |  80 ++++++
>   .../arch/arm64/arm/cortex-a15/exception.json  |   8 +
>   .../arm64/arm/cortex-a15/instruction.json     |  59 +++++
>   .../arch/arm64/arm/cortex-a15/memory.json     |  20 ++
>   .../arch/arm64/arm/cortex-a17/branch.json     |  17 ++
>   .../arch/arm64/arm/cortex-a17/bus.json        |  26 ++
>   .../arch/arm64/arm/cortex-a17/cache.json      |  53 ++++
>   .../arch/arm64/arm/cortex-a17/exception.json  |  11 +
>   .../arm64/arm/cortex-a17/instruction.json     |  56 +++++
>   .../arch/arm64/arm/cortex-a17/memory.json     |  20 ++
>   .../arch/arm64/arm/cortex-a32/branch.json     |  11 +
>   .../arch/arm64/arm/cortex-a32/bus.json        |  17 ++
>   .../arch/arm64/arm/cortex-a32/cache.json      |  32 +++
>   .../arch/arm64/arm/cortex-a32/exception.json  |  14 ++
>   .../arm64/arm/cortex-a32/instruction.json     |  29 +++
>   .../arch/arm64/arm/cortex-a32/memory.json     |   8 +
>   .../arch/arm64/arm/cortex-a34/branch.json     |  11 +
>   .../arch/arm64/arm/cortex-a34/bus.json        |  17 ++
>   .../arch/arm64/arm/cortex-a34/cache.json      |  32 +++
>   .../arch/arm64/arm/cortex-a34/exception.json  |  14 ++
>   .../arm64/arm/cortex-a34/instruction.json     |  29 +++
>   .../arch/arm64/arm/cortex-a34/memory.json     |   8 +
>   .../arch/arm64/arm/cortex-a35/branch.json     |  11 +
>   .../arch/arm64/arm/cortex-a35/bus.json        |  17 ++
>   .../arch/arm64/arm/cortex-a35/cache.json      |  32 +++
>   .../arch/arm64/arm/cortex-a35/exception.json  |  14 ++
>   .../arm64/arm/cortex-a35/instruction.json     |  44 ++++
>   .../arch/arm64/arm/cortex-a35/memory.json     |   8 +
>   .../arch/arm64/arm/cortex-a5/branch.json      |   8 +
>   .../arch/arm64/arm/cortex-a5/cache.json       |  23 ++
>   .../arch/arm64/arm/cortex-a5/exception.json   |  11 +
>   .../arch/arm64/arm/cortex-a5/instruction.json |  29 +++
>   .../arch/arm64/arm/cortex-a5/memory.json      |   8 +
>   .../arch/arm64/arm/cortex-a510/branch.json    |  59 +++++
>   .../arch/arm64/arm/cortex-a510/bus.json       |  17 ++
>   .../arch/arm64/arm/cortex-a510/cache.json     | 182 ++++++++++++++
>   .../arch/arm64/arm/cortex-a510/exception.json |  14 ++
>   .../arm64/arm/cortex-a510/instruction.json    |  95 +++++++
>   .../arch/arm64/arm/cortex-a510/memory.json    |  32 +++
>   .../arch/arm64/arm/cortex-a510/pipeline.json  | 107 ++++++++
>   .../arch/arm64/arm/cortex-a510/pmu.json       |   8 +
>   .../arch/arm64/arm/cortex-a510/trace.json     |  32 +++
>   .../arch/arm64/arm/cortex-a55/branch.json     |  59 +++++
>   .../arch/arm64/arm/cortex-a55/bus.json        |  17 ++
>   .../arch/arm64/arm/cortex-a55/cache.json      | 188 ++++++++++++++
>   .../arch/arm64/arm/cortex-a55/exception.json  |  20 ++
>   .../arm64/arm/cortex-a55/instruction.json     |  65 +++++
>   .../arch/arm64/arm/cortex-a55/memory.json     |  17 ++
>   .../arch/arm64/arm/cortex-a55/pipeline.json   |  80 ++++++
>   .../arch/arm64/arm/cortex-a65/branch.json     |  17 ++
>   .../arch/arm64/arm/cortex-a65/bus.json        |  17 ++
>   .../arch/arm64/arm/cortex-a65/cache.json      | 236 ++++++++++++++++++
>   .../arch/arm64/arm/cortex-a65/dpu.json        |  32 +++
>   .../arch/arm64/arm/cortex-a65/exception.json  |  14 ++
>   .../arch/arm64/arm/cortex-a65/ifu.json        | 122 +++++++++
>   .../arm64/arm/cortex-a65/instruction.json     |  71 ++++++
>   .../arch/arm64/arm/cortex-a65/memory.json     |  35 +++
>   .../arch/arm64/arm/cortex-a65/pipeline.json   |   8 +
>   .../arch/arm64/arm/cortex-a7/branch.json      |   8 +
>   .../arch/arm64/arm/cortex-a7/bus.json         |  17 ++
>   .../arch/arm64/arm/cortex-a7/cache.json       |  32 +++
>   .../arch/arm64/arm/cortex-a7/exception.json   |  11 +
>   .../arch/arm64/arm/cortex-a7/instruction.json |  29 +++
>   .../arch/arm64/arm/cortex-a7/memory.json      |   8 +
>   .../arch/arm64/arm/cortex-a710/branch.json    |  17 ++
>   .../arch/arm64/arm/cortex-a710/bus.json       |  20 ++
>   .../arch/arm64/arm/cortex-a710/cache.json     | 155 ++++++++++++
>   .../arch/arm64/arm/cortex-a710/exception.json |  47 ++++
>   .../arm64/arm/cortex-a710/instruction.json    | 134 ++++++++++
>   .../arch/arm64/arm/cortex-a710/memory.json    |  41 +++
>   .../arch/arm64/arm/cortex-a710/pipeline.json  |  23 ++
>   .../arch/arm64/arm/cortex-a710/trace.json     |  29 +++
>   .../arch/arm64/arm/cortex-a73/branch.json     |  11 +
>   .../arch/arm64/arm/cortex-a73/bus.json        |  23 ++
>   .../arch/arm64/arm/cortex-a73/cache.json      | 107 ++++++++
>   .../arch/arm64/arm/cortex-a73/etm.json        |  14 ++
>   .../arch/arm64/arm/cortex-a73/exception.json  |  14 ++
>   .../arm64/arm/cortex-a73/instruction.json     |  65 +++++
>   .../arch/arm64/arm/cortex-a73/memory.json     |  14 ++
>   .../arch/arm64/arm/cortex-a73/mmu.json        |  44 ++++
>   .../arch/arm64/arm/cortex-a73/pipeline.json   |  38 +++
>   .../arch/arm64/arm/cortex-a75/branch.json     |  11 +
>   .../arch/arm64/arm/cortex-a75/bus.json        |  17 ++
>   .../arch/arm64/arm/cortex-a75/cache.json      | 164 ++++++++++++
>   .../arch/arm64/arm/cortex-a75/etm.json        |  14 ++
>   .../arch/arm64/arm/cortex-a75/exception.json  |  17 ++
>   .../arm64/arm/cortex-a75/instruction.json     |  74 ++++++
>   .../arch/arm64/arm/cortex-a75/memory.json     |  17 ++
>   .../arch/arm64/arm/cortex-a75/mmu.json        |  44 ++++
>   .../arch/arm64/arm/cortex-a75/pipeline.json   |  44 ++++
>   .../arch/arm64/arm/cortex-a77/branch.json     |  17 ++
>   .../arch/arm64/arm/cortex-a77/bus.json        |  17 ++
>   .../arch/arm64/arm/cortex-a77/cache.json      | 143 +++++++++++
>   .../arch/arm64/arm/cortex-a77/exception.json  |  47 ++++
>   .../arm64/arm/cortex-a77/instruction.json     |  77 ++++++
>   .../arch/arm64/arm/cortex-a77/memory.json     |  23 ++
>   .../arch/arm64/arm/cortex-a77/pipeline.json   |   8 +
>   .../arch/arm64/arm/cortex-a78/branch.json     |  17 ++
>   .../arch/arm64/arm/cortex-a78/bus.json        |  20 ++
>   .../arch/arm64/arm/cortex-a78/cache.json      | 155 ++++++++++++
>   .../arch/arm64/arm/cortex-a78/exception.json  |  47 ++++
>   .../arm64/arm/cortex-a78/instruction.json     |  80 ++++++
>   .../arch/arm64/arm/cortex-a78/memory.json     |  23 ++
>   .../arch/arm64/arm/cortex-a78/pipeline.json   |  23 ++
>   .../arch/arm64/arm/cortex-a8/branch.json      |   8 +
>   .../arch/arm64/arm/cortex-a8/cache.json       |  77 ++++++
>   .../arch/arm64/arm/cortex-a8/exception.json   |   5 +
>   .../arch/arm64/arm/cortex-a8/instruction.json |  38 +++
>   .../arch/arm64/arm/cortex-a8/memory.json      |   5 +
>   .../arch/arm64/arm/cortex-a9/branch.json      |   8 +
>   .../arch/arm64/arm/cortex-a9/cache.json       |  17 ++
>   .../arch/arm64/arm/cortex-a9/exception.json   |   5 +
>   .../arch/arm64/arm/cortex-a9/instruction.json |  29 +++
>   .../arch/arm64/arm/cortex-a9/memory.json      |   5 +
>   .../arch/arm64/arm/cortex-x1/branch.json      |  17 ++
>   .../arch/arm64/arm/cortex-x1/bus.json         |  20 ++
>   .../arch/arm64/arm/cortex-x1/cache.json       | 155 ++++++++++++
>   .../arch/arm64/arm/cortex-x1/exception.json   |  47 ++++
>   .../arch/arm64/arm/cortex-x1/instruction.json |  80 ++++++
>   .../arch/arm64/arm/cortex-x1/memory.json      |  23 ++
>   .../arch/arm64/arm/cortex-x1/pipeline.json    |  23 ++
>   .../arch/arm64/arm/cortex-x2/branch.json      |  17 ++
>   .../arch/arm64/arm/cortex-x2/bus.json         |  20 ++
>   .../arch/arm64/arm/cortex-x2/cache.json       | 155 ++++++++++++
>   .../arch/arm64/arm/cortex-x2/exception.json   |  47 ++++
>   .../arch/arm64/arm/cortex-x2/instruction.json | 134 ++++++++++
>   .../arch/arm64/arm/cortex-x2/memory.json      |  41 +++
>   .../arch/arm64/arm/cortex-x2/pipeline.json    |  23 ++
>   .../arch/arm64/arm/cortex-x2/trace.json       |  29 +++
>   .../arch/arm64/arm/neoverse-e1/branch.json    |  17 ++
>   .../arch/arm64/arm/neoverse-e1/bus.json       |  17 ++
>   .../arch/arm64/arm/neoverse-e1/cache.json     | 107 ++++++++
>   .../arch/arm64/arm/neoverse-e1/exception.json |  14 ++
>   .../arm64/arm/neoverse-e1/instruction.json    |  65 +++++
>   .../arch/arm64/arm/neoverse-e1/memory.json    |  23 ++
>   .../arch/arm64/arm/neoverse-e1/pipeline.json  |   8 +
>   .../arch/arm64/arm/neoverse-e1/spe.json       |  14 ++
>   .../arch/arm64/common-and-microarch.json      |  66 +++++
>   tools/perf/pmu-events/arch/arm64/mapfile.csv  |  20 ++
>   141 files changed, 5746 insertions(+)
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/branch.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/bus.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/cache.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/exception.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/instruction.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/memory.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/branch.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/bus.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/cache.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/exception.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/instruction.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/memory.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/branch.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/bus.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/cache.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/exception.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/instruction.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/memory.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/branch.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/bus.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/cache.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/exception.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/instruction.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/memory.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/branch.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/bus.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/cache.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/exception.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/instruction.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/memory.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a5/branch.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a5/cache.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a5/exception.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a5/instruction.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a5/memory.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/branch.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/bus.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/cache.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/exception.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/instruction.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/memory.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/pipeline.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/pmu.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/trace.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/branch.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/bus.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/cache.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/exception.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/instruction.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/memory.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/pipeline.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/branch.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/bus.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/cache.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/dpu.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/exception.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/ifu.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/instruction.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/memory.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/pipeline.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/branch.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/bus.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/cache.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/exception.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/instruction.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/memory.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/branch.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/bus.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/cache.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/exception.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/instruction.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/memory.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/pipeline.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/trace.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/branch.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/bus.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/cache.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/etm.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/exception.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/instruction.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/memory.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/mmu.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/pipeline.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/branch.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/bus.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/cache.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/etm.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/exception.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/instruction.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/memory.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/mmu.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/pipeline.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/branch.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/bus.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/cache.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/exception.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/instruction.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/memory.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/pipeline.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/branch.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/bus.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/cache.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/exception.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/instruction.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/memory.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/pipeline.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/branch.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/cache.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/exception.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/instruction.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/memory.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/branch.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/cache.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/exception.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/instruction.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/memory.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/branch.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/bus.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/cache.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/exception.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/instruction.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/memory.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/pipeline.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/branch.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/bus.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/cache.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/exception.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/instruction.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/memory.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/pipeline.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/trace.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/branch.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/bus.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/cache.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/exception.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/instruction.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/memory.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/pipeline.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/spe.json
>

On 17/05/2022 15:32, Robin Murphy wrote:
> 
> On 2022-05-10 11:47, Nick Forrington wrote:
>> Add Performance Monitoring Unit event data for the Arm CPUs listed
>> below.
>>
>> Changesets are dependent due to incremental updates to the common events
>> file and mapfile.csv.
>>
>> Data is sourced from https://github.com/ARM-software/data
>>
>> Nick Forrington (20):
>>    perf vendors events arm64: Arm Cortex-A5
>>    perf vendors events arm64: Arm Cortex-A7
>>    perf vendors events arm64: Arm Cortex-A8
>>    perf vendors events arm64: Arm Cortex-A9
>>    perf vendors events arm64: Arm Cortex-A15
>>    perf vendors events arm64: Arm Cortex-A17
>>    perf vendors events arm64: Arm Cortex-A32
> 
> Obligatory question over anything relating to the above CPUs being in an 
> "arch/arm64" directory... ;)

If we were to add to arm32/arm then the common event numbers and maybe 
other JSONs in future would need to be duplicated.

Would there be any reason to add to arm32/arm apart to from being 
strictly proper? Maybe if lots of other 32b support for other vendors 
came along then it could make sense (to separate them out).

thanks,
John

On 18/05/2022 09:15, John Garry wrote:
> On 17/05/2022 15:32, Robin Murphy wrote:
>>
>> On 2022-05-10 11:47, Nick Forrington wrote:
>>> Add Performance Monitoring Unit event data for the Arm CPUs listed
>>> below.
>>>
>>> Changesets are dependent due to incremental updates to the common 
>>> events
>>> file and mapfile.csv.
>>>
>>> Data is sourced from https://github.com/ARM-software/data
>>>
>>> Nick Forrington (20):
>>>    perf vendors events arm64: Arm Cortex-A5
>>>    perf vendors events arm64: Arm Cortex-A7
>>>    perf vendors events arm64: Arm Cortex-A8
>>>    perf vendors events arm64: Arm Cortex-A9
>>>    perf vendors events arm64: Arm Cortex-A15
>>>    perf vendors events arm64: Arm Cortex-A17
>>>    perf vendors events arm64: Arm Cortex-A32
>>
>> Obligatory question over anything relating to the above CPUs being in 
>> an "arch/arm64" directory... ;)
>
> If we were to add to arm32/arm then the common event numbers and maybe 
> other JSONs in future would need to be duplicated.
>
> Would there be any reason to add to arm32/arm apart to from being 
> strictly proper? Maybe if lots of other 32b support for other vendors 
> came along then it could make sense (to separate them out).

Not that I'm aware of, although I don't have these available to test.

I'm happy to re-submit without these CPUs if it simplifies things.

Thanks,
Nick

On 2022-05-18 09:15, John Garry wrote:
> On 17/05/2022 15:32, Robin Murphy wrote:
>>
>> On 2022-05-10 11:47, Nick Forrington wrote:
>>> Add Performance Monitoring Unit event data for the Arm CPUs listed
>>> below.
>>>
>>> Changesets are dependent due to incremental updates to the common events
>>> file and mapfile.csv.
>>>
>>> Data is sourced from https://github.com/ARM-software/data
>>>
>>> Nick Forrington (20):
>>>    perf vendors events arm64: Arm Cortex-A5
>>>    perf vendors events arm64: Arm Cortex-A7
>>>    perf vendors events arm64: Arm Cortex-A8
>>>    perf vendors events arm64: Arm Cortex-A9
>>>    perf vendors events arm64: Arm Cortex-A15
>>>    perf vendors events arm64: Arm Cortex-A17
>>>    perf vendors events arm64: Arm Cortex-A32
>>
>> Obligatory question over anything relating to the above CPUs being in 
>> an "arch/arm64" directory... ;)
> 
> If we were to add to arm32/arm then the common event numbers and maybe 
> other JSONs in future would need to be duplicated.
> 
> Would there be any reason to add to arm32/arm apart to from being 
> strictly proper? Maybe if lots of other 32b support for other vendors 
> came along then it could make sense (to separate them out).

That's the heart of the question, really. At best it seems unnecessarily 
confusing as-is. AFAICS either the naming isn't functional, wherein it 
would potentially make the most sense to rename the whole thing 
"pmu-events/arch/arm" if it's merely for categorising Arm architectures 
in general, or it is actually tied to the host triplet, in which case 
the above patches are most likely useless.

I'd agree that there doesn't seem much point in trying to separate 
things along relatively arbitrary lines if it *isn't* functionally 
necessary - the PMUv2 common events look to be a straightforward subset 
of the PMUv3 ones, but then there's Cortex-A32 anyway, plus most of the 
already-supported CPUs could equally run an AArch32 perf tool as well.

Thanks,
Robin.

On 18/05/2022 13:32, Robin Murphy wrote:
>> If we were to add to arm32/arm then the common event numbers and maybe 
>> other JSONs in future would need to be duplicated.
>>
>> Would there be any reason to add to arm32/arm apart to from being 
>> strictly proper? Maybe if lots of other 32b support for other vendors 
>> came along then it could make sense (to separate them out).
> 
> That's the heart of the question, really. At best it seems unnecessarily 
> confusing as-is. 

I think it comes down to the first core supported was TX2 and the build 
system relies on the target arch to decide which arch from 
pmu-events/arch to compile.

> AFAICS either the naming isn't functional, wherein it 
> would potentially make the most sense to rename the whole thing 
> "pmu-events/arch/arm" if it's merely for categorising Arm architectures 
> in general, or it is actually tied to the host triplet, in which case 
> the above patches are most likely useless.

Today ARCH=arm has no pmu-events support. I think that it should be easy 
to add plumbing for that. It becomes more tricky with supporting a 
single "arm" folder.

But then do people really care enough about pmu-events for these 32b 
cores? Until now, it seems not.

> 
> I'd agree that there doesn't seem much point in trying to separate 
> things along relatively arbitrary lines if it *isn't* functionally 
> necessary - the PMUv2 common events look to be a straightforward subset 
> of the PMUv3 ones, but then there's Cortex-A32 anyway, plus most of the 
> already-supported CPUs could equally run an AArch32 perf tool as well.

Sure, we should have these 32b cores supported for ARCH=arm if they are 
supported for ARCH=arm64. But then does it even make sense to have A7 
support in arch/arm64?

Thanks,
John

On 2022-05-18 14:48, John Garry wrote:
> On 18/05/2022 13:32, Robin Murphy wrote:
>>> If we were to add to arm32/arm then the common event numbers and 
>>> maybe other JSONs in future would need to be duplicated.
>>>
>>> Would there be any reason to add to arm32/arm apart to from being 
>>> strictly proper? Maybe if lots of other 32b support for other vendors 
>>> came along then it could make sense (to separate them out).
>>
>> That's the heart of the question, really. At best it seems 
>> unnecessarily confusing as-is. 
> 
> I think it comes down to the first core supported was TX2 and the build 
> system relies on the target arch to decide which arch from 
> pmu-events/arch to compile.
> 
>> AFAICS either the naming isn't functional, wherein it would 
>> potentially make the most sense to rename the whole thing 
>> "pmu-events/arch/arm" if it's merely for categorising Arm 
>> architectures in general, or it is actually tied to the host triplet, 
>> in which case the above patches are most likely useless.
> 
> Today ARCH=arm has no pmu-events support. I think that it should be easy 
> to add plumbing for that. It becomes more tricky with supporting a 
> single "arm" folder.
> 
> But then do people really care enough about pmu-events for these 32b 
> cores? Until now, it seems not.
> 
>>
>> I'd agree that there doesn't seem much point in trying to separate 
>> things along relatively arbitrary lines if it *isn't* functionally 
>> necessary - the PMUv2 common events look to be a straightforward 
>> subset of the PMUv3 ones, but then there's Cortex-A32 anyway, plus 
>> most of the already-supported CPUs could equally run an AArch32 perf 
>> tool as well.
> 
> Sure, we should have these 32b cores supported for ARCH=arm if they are 
> supported for ARCH=arm64. But then does it even make sense to have A7 
> support in arch/arm64?

That's what I'm getting at. If it is tied to the build target as you've 
said above, then there is no point in an AArch64 perf tool including 
data for CPUs on which that tool cannot possibly run; it's simply a 
waste of space.

If there is interest in plumbing in support on AArch32 builds as well, 
then I'd still be inclined to have a single arch/arm events directory, 
and either do some build-time path munging or just symlink an arch/arm64 
sibling back to it. Yes, technically there are AArch64-only CPUs whose 
data would then be redundant when building for AArch32, but those are 
such a minority that it seems like an entirely reasonable compromise.

Thanks,
Robin.

On 18/05/2022 15:14, Robin Murphy wrote:
>> Sure, we should have these 32b cores supported for ARCH=arm if they 
>> are supported for ARCH=arm64. But then does it even make sense to have 
>> A7 support in arch/arm64?
> 
> That's what I'm getting at. If it is tied to the build target as you've 
> said above, then there is no point in an AArch64 perf tool including 
> data for CPUs on which that tool cannot possibly run; it's simply a 
> waste of space.
> 
> If there is interest in plumbing in support on AArch32 builds as well, 
> then I'd still be inclined to have a single arch/arm events directory, 
> and either do some build-time path munging or just symlink an arch/arm64 
> sibling back to it. Yes, technically there are AArch64-only CPUs whose 
> data would then be redundant when building for AArch32, 

If size is an issue then we have ways to cut this down, like doing the 
arch standard events fixup dynamically when running perf tool, or even 
not describing those events in the JSONs and rely on reading the CPU PMU 
events folder to learn which of those events are supported.

 > but those are
 > such a minority that it seems like an entirely reasonable compromise.

@Nick, Can you drop the 32b core support for arm64? Or, if you really 
want them, look into ARCH=arm pmu-events support?

thanks,
John

On 19/05/2022 08:59, John Garry wrote:
> On 18/05/2022 15:14, Robin Murphy wrote:
>>> Sure, we should have these 32b cores supported for ARCH=arm if they 
>>> are supported for ARCH=arm64. But then does it even make sense to 
>>> have A7 support in arch/arm64?
>>
>> That's what I'm getting at. If it is tied to the build target as 
>> you've said above, then there is no point in an AArch64 perf tool 
>> including data for CPUs on which that tool cannot possibly run; it's 
>> simply a waste of space.
>>
>> If there is interest in plumbing in support on AArch32 builds as 
>> well, then I'd still be inclined to have a single arch/arm events 
>> directory, and either do some build-time path munging or just symlink 
>> an arch/arm64 sibling back to it. Yes, technically there are 
>> AArch64-only CPUs whose data would then be redundant when building 
>> for AArch32, 
>
> If size is an issue then we have ways to cut this down, like doing the 
> arch standard events fixup dynamically when running perf tool, or even 
> not describing those events in the JSONs and rely on reading the CPU 
> PMU events folder to learn which of those events are supported.
>
> > but those are
> > such a minority that it seems like an entirely reasonable compromise.
>
> @Nick, Can you drop the 32b core support for arm64? Or, if you really 
> want them, look into ARCH=arm pmu-events support?

No problem - I'll resubmit without the 32b-only CPUs.

Thanks,
Nick

On Thu, May 19, 2022 at 6:53 AM Nick Forrington <nick.forrington@arm.com> wrote:
>
>
> On 19/05/2022 08:59, John Garry wrote:
> > On 18/05/2022 15:14, Robin Murphy wrote:
> >>> Sure, we should have these 32b cores supported for ARCH=arm if they
> >>> are supported for ARCH=arm64. But then does it even make sense to
> >>> have A7 support in arch/arm64?
> >>
> >> That's what I'm getting at. If it is tied to the build target as
> >> you've said above, then there is no point in an AArch64 perf tool
> >> including data for CPUs on which that tool cannot possibly run; it's
> >> simply a waste of space.
> >>
> >> If there is interest in plumbing in support on AArch32 builds as
> >> well, then I'd still be inclined to have a single arch/arm events
> >> directory, and either do some build-time path munging or just symlink
> >> an arch/arm64 sibling back to it. Yes, technically there are
> >> AArch64-only CPUs whose data would then be redundant when building
> >> for AArch32,
> >
> > If size is an issue then we have ways to cut this down, like doing the
> > arch standard events fixup dynamically when running perf tool, or even
> > not describing those events in the JSONs and rely on reading the CPU
> > PMU events folder to learn which of those events are supported.
> >
> > > but those are
> > > such a minority that it seems like an entirely reasonable compromise.
> >
> > @Nick, Can you drop the 32b core support for arm64? Or, if you really
> > want them, look into ARCH=arm pmu-events support?
>
> No problem - I'll resubmit without the 32b-only CPUs.
>
> Thanks,
> Nick
>

I'm hoping with jevents.py [1] then we can do a few things on the size front:

1) relocations - the current pattern of generating '.foo = "foo_Bar"'
means that when perf starts the .foo pointer needs to be updated for
the relocation. If we concatenate the strings together then we can
have 1 relocation, but we'll need an offset and length to get .foo's
value and some kind of iteration abstraction. If we do this then we
could also look to compress the string at compile time.
2) sorting events - not really a compiler size improvement but should
lower some runtime memory usage. We shouldn't need to linearly search
event names, sorting at compile time means we can locate faster, less
paging, etc.
3) we've spoken in the past of the problems of cross-architecture
testing of events, metrics, etc. For metrics, we may want to record
events on one architecture and compute metrics on another. One idea is
to have a fuller jevents mode where everything is built into one
binary, which would make size improvements more valuable.

Another thing with jevents.py is trying to make the pmu-events.c
presentation more consistent with sysfs', which may regress things on
size.

Anyway, I think it is good to have more events and I'm excited to see
this merged in a way that's suitable for John. I'm happy to do more
optionality stuff with jevents.py or the build if that can mean having
more events on ARM32.

Thanks,
Ian

[1] https://lore.kernel.org/linux-perf-users/20220511211526.1021908-1-irogers@google.com/
- show your love with Acked-bys :-D