Remove a repeated CPG_SIPLL5_CLK1_REFDIV_WEN.

Signed-off-by: Guo Zhengkui <guozhengkui@vivo.com>
---
 drivers/clk/renesas/rzg2l-cpg.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 15412cc58337..24d752ca1906 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -601,9 +601,8 @@ static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
 
 	/* Output clock setting 1 */
 	writel(CPG_SIPLL5_CLK1_POSTDIV1_WEN | CPG_SIPLL5_CLK1_REFDIV_WEN |
-	       CPG_SIPLL5_CLK1_REFDIV_WEN  | (params.pl5_postdiv1 << 0) |
-	       (params.pl5_postdiv2 << 4) | (params.pl5_refdiv << 8),
-	       priv->base + CPG_SIPLL5_CLK1);
+	       (params.pl5_postdiv1 << 0) | (params.pl5_postdiv2 << 4) |
+	       (params.pl5_refdiv << 8), priv->base + CPG_SIPLL5_CLK1);
 
 	/* Output clock setting, SSCG modulation value setting 3 */
 	writel((params.pl5_fracin << 8), priv->base + CPG_SIPLL5_CLK3);
-- 
2.20.1

Hi Guo,

On Wed, May 4, 2022 at 4:24 PM Guo Zhengkui <guozhengkui@vivo.com> wrote:
> Remove a repeated CPG_SIPLL5_CLK1_REFDIV_WEN.
>
> Signed-off-by: Guo Zhengkui <guozhengkui@vivo.com>

Thanks for your patch!

> --- a/drivers/clk/renesas/rzg2l-cpg.c
> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> @@ -601,9 +601,8 @@ static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
>
>         /* Output clock setting 1 */
>         writel(CPG_SIPLL5_CLK1_POSTDIV1_WEN | CPG_SIPLL5_CLK1_REFDIV_WEN |
> -              CPG_SIPLL5_CLK1_REFDIV_WEN  | (params.pl5_postdiv1 << 0) |

This is not correct: one of the CPG_SIPLL5_CLK1_REFDIV_WENs
should have been CPG_SIPLL5_CLK1_POSTDIV2_WEN.

> -              (params.pl5_postdiv2 << 4) | (params.pl5_refdiv << 8),
> -              priv->base + CPG_SIPLL5_CLK1);
> +              (params.pl5_postdiv1 << 0) | (params.pl5_postdiv2 << 4) |
> +              (params.pl5_refdiv << 8), priv->base + CPG_SIPLL5_CLK1);
>
>         /* Output clock setting, SSCG modulation value setting 3 */
>         writel((params.pl5_fracin << 8), priv->base + CPG_SIPLL5_CLK3);


So I'm going for Wan's fix instead
https://lore.kernel.org/r/20220504142058.18704-1-wanjiabing@vivo.com/

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds