From: Xinlei Lee <xinlei.lee@mediatek.com>
Convert mediatek,dsi.txt to mediatek,dsi.yaml format
Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
.../display/mediatek/mediatek,dsi.txt | 62 ----------
.../display/mediatek/mediatek,dsi.yaml | 115 ++++++++++++++++++
2 files changed, 115 insertions(+), 62 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
deleted file mode 100644
index 36b01458f45c..000000000000
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ /dev/null
@@ -1,62 +0,0 @@
-Mediatek DSI Device
-===================
-
-The Mediatek DSI function block is a sink of the display subsystem and can
-drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
-channel output.
-
-Required properties:
-- compatible: "mediatek,<chip>-dsi"
-- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
-- reg: Physical base address and length of the controller's registers
-- interrupts: The interrupt signal from the function block.
-- clocks: device clocks
- See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
-- clock-names: must contain "engine", "digital", and "hs"
-- phys: phandle link to the MIPI D-PHY controller.
-- phy-names: must contain "dphy"
-- port: Output port node with endpoint definitions as described in
- Documentation/devicetree/bindings/graph.txt. This port should be connected
- to the input port of an attached DSI panel or DSI-to-eDP encoder chip.
-
-Optional properties:
-- resets: list of phandle + reset specifier pair, as described in [1].
-
-[1] Documentation/devicetree/bindings/reset/reset.txt
-
-MIPI TX Configuration Module
-============================
-
-See phy/mediatek,dsi-phy.yaml
-
-Example:
-
-mipi_tx0: mipi-dphy@10215000 {
- compatible = "mediatek,mt8173-mipi-tx";
- reg = <0 0x10215000 0 0x1000>;
- clocks = <&clk26m>;
- clock-output-names = "mipi_tx0_pll";
- #clock-cells = <0>;
- #phy-cells = <0>;
- drive-strength-microamp = <4600>;
- nvmem-cells= <&mipi_tx_calibration>;
- nvmem-cell-names = "calibration-data";
-};
-
-dsi0: dsi@1401b000 {
- compatible = "mediatek,mt8173-dsi";
- reg = <0 0x1401b000 0 0x1000>;
- interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>,
- <&mipi_tx0>;
- clock-names = "engine", "digital", "hs";
- resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
- phys = <&mipi_tx0>;
- phy-names = "dphy";
-
- port {
- dsi0_out: endpoint {
- remote-endpoint = <&panel_in>;
- };
- };
-};
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
new file mode 100644
index 000000000000..fa5bdf28668a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek DSI Controller Device Tree Bindings
+
+maintainers:
+ - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+ - Philipp Zabel <p.zabel@pengutronix.de>
+ - Jitao Shi <jitao.shi@mediatek.com>
+ - Xinlei Lee <xinlei.lee@mediatek.com>
+
+description: |
+ The MediaTek DSI function block is a sink of the display subsystem and can
+ drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
+ channel output.
+
+allOf:
+ - $ref: /schemas/display/dsi-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt2701-dsi
+ - mediatek,mt7623-dsi
+ - mediatek,mt8167-dsi
+ - mediatek,mt8173-dsi
+ - mediatek,mt8183-dsi
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Engine Clock
+ - description: Digital Clock
+ - description: HS Clock
+
+ clock-names:
+ items:
+ - const: engine
+ - const: digital
+ - const: hs
+
+ resets:
+ maxItems: 1
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ items:
+ - const: dphy
+
+ port:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Output port node. This port should be connected to the input
+ port of an attached DSI panel or DSI-to-eDP encoder chip.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - clocks
+ - clock-names
+ - phys
+ - phy-names
+ - port
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/mt8183-power.h>
+ #include <dt-bindings/phy/phy.h>
+ #include <dt-bindings/reset/mt8183-resets.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ dsi0: dsi@14014000 {
+ compatible = "mediatek,mt8183-dsi";
+ reg = <0 0x14014000 0 0x1000>;
+ interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DSI0_MM>,
+ <&mmsys CLK_MM_DSI0_IF>,
+ <&mipi_tx0>;
+ clock-names = "engine", "digital", "hs";
+ resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
+ phys = <&mipi_tx0>;
+ phy-names = "dphy";
+ port {
+ dsi0_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
+
+...
--
2.18.0
Hi, Rex: On Wed, 2022-05-04 at 17:19 +0800, Rex-BC Chen wrote: > From: Xinlei Lee <xinlei.lee@mediatek.com> > > Convert mediatek,dsi.txt to mediatek,dsi.yaml format Reviewed-by: CK Hu <ck.hu@mediatek.com> > > Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> > --- > .../display/mediatek/mediatek,dsi.txt | 62 ---------- > .../display/mediatek/mediatek,dsi.yaml | 115 > ++++++++++++++++++ > 2 files changed, 115 insertions(+), 62 deletions(-) > delete mode 100644 > Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > create mode 100644 > Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml > > diff --git > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > deleted file mode 100644 > index 36b01458f45c..000000000000 > --- > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > +++ /dev/null > @@ -1,62 +0,0 @@ > -Mediatek DSI Device > -=================== > - > -The Mediatek DSI function block is a sink of the display subsystem > and can > -drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for > dual- > -channel output. > - > -Required properties: > -- compatible: "mediatek,<chip>-dsi" > -- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183. > -- reg: Physical base address and length of the controller's > registers > -- interrupts: The interrupt signal from the function block. > -- clocks: device clocks > - See Documentation/devicetree/bindings/clock/clock-bindings.txt for > details. > -- clock-names: must contain "engine", "digital", and "hs" > -- phys: phandle link to the MIPI D-PHY controller. > -- phy-names: must contain "dphy" > -- port: Output port node with endpoint definitions as described in > - Documentation/devicetree/bindings/graph.txt. This port should be > connected > - to the input port of an attached DSI panel or DSI-to-eDP encoder > chip. > - > -Optional properties: > -- resets: list of phandle + reset specifier pair, as described in > [1]. > - > -[1] Documentation/devicetree/bindings/reset/reset.txt > - > -MIPI TX Configuration Module > -============================ > - > -See phy/mediatek,dsi-phy.yaml > - > -Example: > - > -mipi_tx0: mipi-dphy@10215000 { > - compatible = "mediatek,mt8173-mipi-tx"; > - reg = <0 0x10215000 0 0x1000>; > - clocks = <&clk26m>; > - clock-output-names = "mipi_tx0_pll"; > - #clock-cells = <0>; > - #phy-cells = <0>; > - drive-strength-microamp = <4600>; > - nvmem-cells= <&mipi_tx_calibration>; > - nvmem-cell-names = "calibration-data"; > -}; > - > -dsi0: dsi@1401b000 { > - compatible = "mediatek,mt8173-dsi"; > - reg = <0 0x1401b000 0 0x1000>; > - interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; > - clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>, > - <&mipi_tx0>; > - clock-names = "engine", "digital", "hs"; > - resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; > - phys = <&mipi_tx0>; > - phy-names = "dphy"; > - > - port { > - dsi0_out: endpoint { > - remote-endpoint = <&panel_in>; > - }; > - }; > -}; > diff --git > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yam > l > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yam > l > new file mode 100644 > index 000000000000..fa5bdf28668a > --- /dev/null > +++ > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yam > l > @@ -0,0 +1,115 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: > https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml*__;Iw!!CTRNKA9wMg0ARbw!zKJCSsOqM0Bn_efj50JX_HvOItJ8ZUdgh54drCoUdMkmnmVb5pH4pd-gj5RZUQ$ > > +$schema: > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!zKJCSsOqM0Bn_efj50JX_HvOItJ8ZUdgh54drCoUdMkmnmVb5pH4pd8zHOMcVQ$ > > + > +title: MediaTek DSI Controller Device Tree Bindings > + > +maintainers: > + - Chun-Kuang Hu <chunkuang.hu@kernel.org> > + - Philipp Zabel <p.zabel@pengutronix.de> > + - Jitao Shi <jitao.shi@mediatek.com> > + - Xinlei Lee <xinlei.lee@mediatek.com> > + > +description: | > + The MediaTek DSI function block is a sink of the display subsystem > and can > + drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized > for dual- > + channel output. > + > +allOf: > + - $ref: /schemas/display/dsi-controller.yaml# > + > +properties: > + compatible: > + enum: > + - mediatek,mt2701-dsi > + - mediatek,mt7623-dsi > + - mediatek,mt8167-dsi > + - mediatek,mt8173-dsi > + - mediatek,mt8183-dsi > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + clocks: > + items: > + - description: Engine Clock > + - description: Digital Clock > + - description: HS Clock > + > + clock-names: > + items: > + - const: engine > + - const: digital > + - const: hs > + > + resets: > + maxItems: 1 > + > + phys: > + maxItems: 1 > + > + phy-names: > + items: > + - const: dphy > + > + port: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output port node. This port should be connected to the input > + port of an attached DSI panel or DSI-to-eDP encoder chip. > + > +required: > + - compatible > + - reg > + - interrupts > + - power-domains > + - clocks > + - clock-names > + - phys > + - phy-names > + - port > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/mt8183-clk.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + #include <dt-bindings/power/mt8183-power.h> > + #include <dt-bindings/phy/phy.h> > + #include <dt-bindings/reset/mt8183-resets.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + dsi0: dsi@14014000 { > + compatible = "mediatek,mt8183-dsi"; > + reg = <0 0x14014000 0 0x1000>; > + interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DSI0_MM>, > + <&mmsys CLK_MM_DSI0_IF>, > + <&mipi_tx0>; > + clock-names = "engine", "digital", "hs"; > + resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>; > + phys = <&mipi_tx0>; > + phy-names = "dphy"; > + port { > + dsi0_out: endpoint { > + remote-endpoint = <&panel_in>; > + }; > + }; > + }; > + }; > + > +...
On Wed, 04 May 2022 17:19:20 +0800, Rex-BC Chen wrote: > From: Xinlei Lee <xinlei.lee@mediatek.com> > > Convert mediatek,dsi.txt to mediatek,dsi.yaml format > > Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> > --- > .../display/mediatek/mediatek,dsi.txt | 62 ---------- > .../display/mediatek/mediatek,dsi.yaml | 115 ++++++++++++++++++ > 2 files changed, 115 insertions(+), 62 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml > Reviewed-by: Rob Herring <robh@kernel.org>
On Wed, 2022-05-04 at 17:19 +0800, Rex-BC Chen wrote: > From: Xinlei Lee <xinlei.lee@mediatek.com> > > Convert mediatek,dsi.txt to mediatek,dsi.yaml format > > Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> > --- > .../display/mediatek/mediatek,dsi.txt | 62 ---------- > .../display/mediatek/mediatek,dsi.yaml | 115 > ++++++++++++++++++ > 2 files changed, 115 insertions(+), 62 deletions(-) > delete mode 100644 > Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > create mode 100644 > Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml > > diff --git > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > deleted file mode 100644 > index 36b01458f45c..000000000000 > --- > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > +++ /dev/null > @@ -1,62 +0,0 @@ > -Mediatek DSI Device > -=================== > - > -The Mediatek DSI function block is a sink of the display subsystem > and can > -drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for > dual- > -channel output. > - > -Required properties: > -- compatible: "mediatek,<chip>-dsi" > -- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183. > -- reg: Physical base address and length of the controller's > registers > -- interrupts: The interrupt signal from the function block. > -- clocks: device clocks > - See Documentation/devicetree/bindings/clock/clock-bindings.txt for > details. > -- clock-names: must contain "engine", "digital", and "hs" > -- phys: phandle link to the MIPI D-PHY controller. > -- phy-names: must contain "dphy" > -- port: Output port node with endpoint definitions as described in > - Documentation/devicetree/bindings/graph.txt. This port should be > connected > - to the input port of an attached DSI panel or DSI-to-eDP encoder > chip. > - > -Optional properties: > -- resets: list of phandle + reset specifier pair, as described in > [1]. > - > -[1] Documentation/devicetree/bindings/reset/reset.txt > - > -MIPI TX Configuration Module > -============================ > - > -See phy/mediatek,dsi-phy.yaml > - > -Example: > - > -mipi_tx0: mipi-dphy@10215000 { > - compatible = "mediatek,mt8173-mipi-tx"; > - reg = <0 0x10215000 0 0x1000>; > - clocks = <&clk26m>; > - clock-output-names = "mipi_tx0_pll"; > - #clock-cells = <0>; > - #phy-cells = <0>; > - drive-strength-microamp = <4600>; > - nvmem-cells= <&mipi_tx_calibration>; > - nvmem-cell-names = "calibration-data"; > -}; > - > -dsi0: dsi@1401b000 { > - compatible = "mediatek,mt8173-dsi"; > - reg = <0 0x1401b000 0 0x1000>; > - interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; > - clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>, > - <&mipi_tx0>; > - clock-names = "engine", "digital", "hs"; > - resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; > - phys = <&mipi_tx0>; > - phy-names = "dphy"; > - > - port { > - dsi0_out: endpoint { > - remote-endpoint = <&panel_in>; > - }; > - }; > -}; > diff --git > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yam > l > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yam > l > new file mode 100644 > index 000000000000..fa5bdf28668a > --- /dev/null > +++ > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yam > l > @@ -0,0 +1,115 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: > http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek DSI Controller Device Tree Bindings > + > +maintainers: > + - Chun-Kuang Hu <chunkuang.hu@kernel.org> > + - Philipp Zabel <p.zabel@pengutronix.de> > + - Jitao Shi <jitao.shi@mediatek.com> > + - Xinlei Lee <xinlei.lee@mediatek.com> > + > +description: | > + The MediaTek DSI function block is a sink of the display subsystem > and can > + drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized > for dual- > + channel output. > + > +allOf: > + - $ref: /schemas/display/dsi-controller.yaml# > + > +properties: > + compatible: > + enum: > + - mediatek,mt2701-dsi > + - mediatek,mt7623-dsi > + - mediatek,mt8167-dsi > + - mediatek,mt8173-dsi > + - mediatek,mt8183-dsi > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + clocks: > + items: > + - description: Engine Clock > + - description: Digital Clock > + - description: HS Clock > + > + clock-names: > + items: > + - const: engine > + - const: digital > + - const: hs > + > + resets: > + maxItems: 1 > + > + phys: > + maxItems: 1 > + > + phy-names: > + items: > + - const: dphy > + > + port: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output port node. This port should be connected to the input > + port of an attached DSI panel or DSI-to-eDP encoder chip. > + > +required: > + - compatible > + - reg > + - interrupts > + - power-domains > + - clocks > + - clock-names > + - phys > + - phy-names > + - port > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/mt8183-clk.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + #include <dt-bindings/power/mt8183-power.h> > + #include <dt-bindings/phy/phy.h> > + #include <dt-bindings/reset/mt8183-resets.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + dsi0: dsi@14014000 { > + compatible = "mediatek,mt8183-dsi"; > + reg = <0 0x14014000 0 0x1000>; > + interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DSI0_MM>, > + <&mmsys CLK_MM_DSI0_IF>, > + <&mipi_tx0>; > + clock-names = "engine", "digital", "hs"; > + resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>; > + phys = <&mipi_tx0>; > + phy-names = "dphy"; > + port { > + dsi0_out: endpoint { > + remote-endpoint = <&panel_in>; > + }; > + }; > + }; > + }; > + > +... Hello Rob and Krzysztof, Can you give us some suggestions for this conversion patch? Thanks! BRs, Rex
On Wed, May 11, 2022 at 2:24 AM Rex-BC Chen <rex-bc.chen@mediatek.com> wrote: > > On Wed, 2022-05-04 at 17:19 +0800, Rex-BC Chen wrote: > > From: Xinlei Lee <xinlei.lee@mediatek.com> > > > > Convert mediatek,dsi.txt to mediatek,dsi.yaml format > > > > Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com> > > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> > > --- > > .../display/mediatek/mediatek,dsi.txt | 62 ---------- > > .../display/mediatek/mediatek,dsi.yaml | 115 > > ++++++++++++++++++ > > 2 files changed, 115 insertions(+), 62 deletions(-) > > delete mode 100644 > > Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > > create mode 100644 > > Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml [...] > Hello Rob and Krzysztof, > > Can you give us some suggestions for this conversion patch? > Thanks! You can check status for yourself by looking at PW[1] where you will see the review queue is currently ~120 patches and goes back to 5/3. If it is in the queue, I will get to it. Rob [1] https://patchwork.ozlabs.org/project/devicetree-bindings/list/
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