arm64: dts: mt7622: specify the L2 cache topology

[PATCH] arm64: dts: mt7622: specify the L2 cache topology

Posted by Rui Salvaterra 2 years, 4 months ago

On an MT7622 system, the kernel complains of not being able to detect the cache
hierarchy of CPU 0. Specify the shared L2 cache node in the device tree, in
order to fix this.

Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
---
 arch/arm64/boot/dts/mediatek/mt7622.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index 6f8cb3ad1e84..3d6eaf6dd078 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -80,6 +80,7 @@ cpu0: cpu@0 {
 			enable-method = "psci";
 			clock-frequency = <1300000000>;
 			cci-control-port = <&cci_control2>;
+			next-level-cache = <&L2>;
 		};
 
 		cpu1: cpu@1 {
@@ -94,6 +95,12 @@ cpu1: cpu@1 {
 			enable-method = "psci";
 			clock-frequency = <1300000000>;
 			cci-control-port = <&cci_control2>;
+			next-level-cache = <&L2>;
+		};
+
+		L2: l2-cache {
+			compatible = "cache";
+			cache-level = <2>;
 		};
 	};
 
-- 
2.36.0

Re: [PATCH] arm64: dts: mt7622: specify the L2 cache topology

Posted by Matthias Brugger 2 years, 4 months ago


On 29/04/2022 00:57, Rui Salvaterra wrote:
> On an MT7622 system, the kernel complains of not being able to detect the cache
> hierarchy of CPU 0. Specify the shared L2 cache node in the device tree, in
> order to fix this.
> 
> Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>

Applied, thanks!

> ---
>   arch/arm64/boot/dts/mediatek/mt7622.dtsi | 7 +++++++
>   1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> index 6f8cb3ad1e84..3d6eaf6dd078 100644
> --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> @@ -80,6 +80,7 @@ cpu0: cpu@0 {
>   			enable-method = "psci";
>   			clock-frequency = <1300000000>;
>   			cci-control-port = <&cci_control2>;
> +			next-level-cache = <&L2>;
>   		};
>   
>   		cpu1: cpu@1 {
> @@ -94,6 +95,12 @@ cpu1: cpu@1 {
>   			enable-method = "psci";
>   			clock-frequency = <1300000000>;
>   			cci-control-port = <&cci_control2>;
> +			next-level-cache = <&L2>;
> +		};
> +
> +		L2: l2-cache {
> +			compatible = "cache";
> +			cache-level = <2>;
>   		};
>   	};
>