This patch adds DT binding documents for Media Data Path 3 (MDP3)
a unit in multimedia system combined with several components and
used for scaling and color format convert.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
---
.../bindings/media/mediatek,mdp3-rdma.yaml | 82 +++++++++++++++++++
.../bindings/media/mediatek,mdp3-rsz.yaml | 61 ++++++++++++++
.../bindings/media/mediatek,mdp3-wrot.yaml | 66 +++++++++++++++
.../bindings/soc/mediatek/mediatek,ccorr.yaml | 54 ++++++++++++
.../bindings/soc/mediatek/mediatek,wdma.yaml | 67 +++++++++++++++
5 files changed, 330 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
new file mode 100644
index 000000000000..ce24eda14cb6
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Read Direct Memory Access
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+ - Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
+
+description: |
+ Mediatek Read Direct Memory Access(RDMA) component used to do read DMA.
+ It contains one line buffer to store the sufficient pixel data, and
+ must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+ for details.
+
+properties:
+ compatible:
+ items:
+ - const: mediatek,mt8183-mdp3-rdma
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: '/schemas/types.yaml#/definitions/phandle-array'
+ maxItems: 1
+ description: |
+ The register of client driver can be configured by gce with
+ 4 arguments defined in this property, such as phandle of gce, subsys id,
+ register offset and size. Each GCE subsys id is mapping to a client
+ defined in the header include/dt-bindings/gce/<chip>-gce.h.
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: RDMA clock
+ - description: RSZ clock
+
+ iommus:
+ maxItems: 1
+
+ mboxes:
+ items:
+ - description: used for 1st data pipe from RDMA
+ - description: used for 2nd data pipe from RDMA
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - power-domains
+ - clocks
+ - iommus
+ - mboxes
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/gce/mt8183-gce.h>
+ #include <dt-bindings/power/mt8183-power.h>
+ #include <dt-bindings/memory/mt8183-larb-port.h>
+
+ mdp3_rdma0: mdp3-rdma0@14001000 {
+ compatible = "mediatek,mt8183-mdp3-rdma";
+ reg = <0x14001000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_RDMA0>,
+ <&mmsys CLK_MM_MDP_RSZ1>;
+ iommus = <&iommu>;
+ mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
+ <&gce 21 CMDQ_THR_PRIO_LOWEST>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
new file mode 100644
index 000000000000..ebc124f86dc9
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-rsz.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Resizer
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+ - Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to do frame resizing.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8183-mdp3-rsz
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ description: The register of client driver can be configured by gce with
+ 4 arguments defined in this property, such as phandle of gce, subsys id,
+ register offset and size. Each GCE subsys id is mapping to a client
+ defined in the header include/dt-bindings/gce/<chip>-gce.h.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/gce/mt8183-gce.h>
+
+ mdp3_rsz0: mdp3-rsz0@14003000 {
+ compatible = "mediatek,mt8183-mdp3-rsz";
+ reg = <0x14003000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ0>;
+ };
+
+ mdp3_rsz1: mdp3-rsz1@14004000 {
+ compatible = "mediatek,mt8183-mdp3-rsz";
+ reg = <0x14004000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ1>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
new file mode 100644
index 000000000000..a19d536d5a9a
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-wrot.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Write DMA with Rotation
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+ - Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to write DMA with frame rotation.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8183-mdp3-wrot
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ description: The register of client driver can be configured by gce with
+ 4 arguments defined in this property, such as phandle of gce, subsys id,
+ register offset and size. Each GCE subsys id is mapping to a client
+ defined in the header include/dt-bindings/gce/<chip>-gce.h.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+
+ iommus:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - power-domains
+ - clocks
+ - iommus
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/gce/mt8183-gce.h>
+ #include <dt-bindings/power/mt8183-power.h>
+ #include <dt-bindings/memory/mt8183-larb-port.h>
+
+ mdp3_wrot0: mdp3-wrot0@14005000 {
+ compatible = "mediatek,mt8183-mdp3-wrot";
+ reg = <0x14005000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_WROT0>;
+ iommus = <&iommu>;
+ };
diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
new file mode 100644
index 000000000000..582f5eff93ec
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/mediatek/mediatek,ccorr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek color correction
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+ - Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
+
+description: |
+ Mediatek color correction with 3X3 matrix.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8183-mdp3-ccorr
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ description: The register of client driver can be configured by gce with
+ 4 arguments defined in this property, such as phandle of gce, subsys id,
+ register offset and size. Each GCE subsys id is mapping to a client
+ defined in the header include/dt-bindings/gce/<chip>-gce.h.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/gce/mt8183-gce.h>
+
+ mdp3_ccorr: mdp3-ccorr@1401c000 {
+ compatible = "mediatek,mt8183-mdp3-ccorr";
+ reg = <0x1401c000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_CCORR>;
+ };
diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
new file mode 100644
index 000000000000..f60c60c5dd81
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/mediatek/mediatek,wdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Write Direct Memory Access
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+ - Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
+
+description: |
+ Mediatek Write Direct Memory Access(WDMA) component used to write
+ the data into DMA.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8183-mdp3-wdma
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ description: The register of client driver can be configured by gce with
+ 4 arguments defined in this property, such as phandle of gce, subsys id,
+ register offset and size. Each GCE subsys id is mapping to a client
+ defined in the header include/dt-bindings/gce/<chip>-gce.h.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+
+ iommus:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - power-domains
+ - clocks
+ - iommus
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/gce/mt8183-gce.h>
+ #include <dt-bindings/power/mt8183-power.h>
+ #include <dt-bindings/memory/mt8183-larb-port.h>
+
+ mdp3_wdma: mdp3-wdma@14006000 {
+ compatible = "mediatek,mt8183-mdp3-wdma";
+ reg = <0x14006000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_WDMA0>;
+ iommus = <&iommu>;
+ };
--
2.18.0
On Wed, Apr 27, 2022 at 03:05:12PM +0800, Moudy Ho wrote: > This patch adds DT binding documents for Media Data Path 3 (MDP3) > a unit in multimedia system combined with several components and > used for scaling and color format convert. > > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com> > --- > .../bindings/media/mediatek,mdp3-rdma.yaml | 82 +++++++++++++++++++ > .../bindings/media/mediatek,mdp3-rsz.yaml | 61 ++++++++++++++ > .../bindings/media/mediatek,mdp3-wrot.yaml | 66 +++++++++++++++ > .../bindings/soc/mediatek/mediatek,ccorr.yaml | 54 ++++++++++++ > .../bindings/soc/mediatek/mediatek,wdma.yaml | 67 +++++++++++++++ > 5 files changed, 330 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml > create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml > create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml > create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml > create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml > > diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml > new file mode 100644 > index 000000000000..ce24eda14cb6 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml > @@ -0,0 +1,82 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Mediatek Read Direct Memory Access > + > +maintainers: > + - Matthias Brugger <matthias.bgg@gmail.com> > + - Ping-Hsun Wu <ping-hsun.wu@mediatek.com> > + > +description: | > + Mediatek Read Direct Memory Access(RDMA) component used to do read DMA. > + It contains one line buffer to store the sufficient pixel data, and > + must be siblings to the central MMSYS_CONFIG node. > + For a description of the MMSYS_CONFIG binding, see > + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml > + for details. > + > +properties: > + compatible: > + items: > + - const: mediatek,mt8183-mdp3-rdma > + > + reg: > + maxItems: 1 > + > + mediatek,gce-client-reg: > + $ref: '/schemas/types.yaml#/definitions/phandle-array' > + maxItems: 1 Like your other patches this needs 'items' describing each cell. > + description: | > + The register of client driver can be configured by gce with > + 4 arguments defined in this property, such as phandle of gce, subsys id, > + register offset and size. Each GCE subsys id is mapping to a client > + defined in the header include/dt-bindings/gce/<chip>-gce.h. Other than other cases of this property, the rest looks fine. Rob
On Tue, 2022-05-03 at 12:47 -0500, Rob Herring wrote: > On Wed, Apr 27, 2022 at 03:05:12PM +0800, Moudy Ho wrote: > > This patch adds DT binding documents for Media Data Path 3 (MDP3) > > a unit in multimedia system combined with several components and > > used for scaling and color format convert. > > > > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com> > > --- > > .../bindings/media/mediatek,mdp3-rdma.yaml | 82 > > +++++++++++++++++++ > > .../bindings/media/mediatek,mdp3-rsz.yaml | 61 ++++++++++++++ > > .../bindings/media/mediatek,mdp3-wrot.yaml | 66 +++++++++++++++ > > .../bindings/soc/mediatek/mediatek,ccorr.yaml | 54 ++++++++++++ > > .../bindings/soc/mediatek/mediatek,wdma.yaml | 67 +++++++++++++++ > > 5 files changed, 330 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml > > create mode 100644 > > Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml > > create mode 100644 > > Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml > > create mode 100644 > > Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml > > create mode 100644 > > Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml > > > > diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3- > > rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3- > > rdma.yaml > > new file mode 100644 > > index 000000000000..ce24eda14cb6 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3- > > rdma.yaml > > @@ -0,0 +1,82 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml*__;Iw!!CTRNKA9wMg0ARbw!zzzJB6GFgAbOaMvOMeEANc2UnatoXvcdzZ3UGx6024oxx1okemuH9vCeCSpaGUuD8dSrlYueRf2HFVdfFu6CVB7LUQ$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!zzzJB6GFgAbOaMvOMeEANc2UnatoXvcdzZ3UGx6024oxx1okemuH9vCeCSpaGUuD8dSrlYueRf2HFVdfFu5BwY-loQ$ > > > > + > > +title: Mediatek Read Direct Memory Access > > + > > +maintainers: > > + - Matthias Brugger <matthias.bgg@gmail.com> > > + - Ping-Hsun Wu <ping-hsun.wu@mediatek.com> > > + > > +description: | > > + Mediatek Read Direct Memory Access(RDMA) component used to do > > read DMA. > > + It contains one line buffer to store the sufficient pixel data, > > and > > + must be siblings to the central MMSYS_CONFIG node. > > + For a description of the MMSYS_CONFIG binding, see > > + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.ya > > ml > > + for details. > > + > > +properties: > > + compatible: > > + items: > > + - const: mediatek,mt8183-mdp3-rdma > > + > > + reg: > > + maxItems: 1 > > + > > + mediatek,gce-client-reg: > > + $ref: '/schemas/types.yaml#/definitions/phandle-array' > > + maxItems: 1 > > Like your other patches this needs 'items' describing each cell. > > > + description: | > > + The register of client driver can be configured by gce with > > + 4 arguments defined in this property, such as phandle of > > gce, subsys id, > > + register offset and size. Each GCE subsys id is mapping to a > > client > > + defined in the header include/dt-bindings/gce/<chip>-gce.h. > > Other than other cases of this property, the rest looks fine. > > Rob Hello Rob, Thanks for your review and reminder. Moudy's mail is still not received by devicetree@vger.kernel.org. We are still under checking this issue. To prevent you do not receive his response, I help Moudy to mail you again. Moudy will sync the description from the patch listed below to this property and extend to other yaml files in this series. https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20220427064425.30383-5-moudy.ho@mediatek.com/ BRs, Rex
© 2016 - 2024 Red Hat, Inc.