When booting a kernel on some Intel CooperLake systems, it was found
that the initial TSC sync at boot up may sometime fail leading to a
fallback to HPET as the system clock instead with some performance
degradation. For example

[    0.034090] TSC deadline timer available
[    0.008807] TSC ADJUST compensate: CPU36 observed 95626 warp. Adjust: 95626
[    0.008807] TSC ADJUST compensate: CPU36 observed 74 warp. Adjust: 95700
[    0.974281] TSC synchronization [CPU#0 -> CPU#36]:
[    0.974281] Measured 4 cycles TSC warp between CPUs, turning off TSC clock.
[    0.974281] tsc: Marking TSC unstable due to check_tsc_sync_source failed

This patch set tries to minimize these type of failures by
 1) Put all the TSC synchronization variables in their own cacheline to
    minimize external interference.
 2) Try to estimate the synchronization overhead and add it to the
    adjustment value.

With these changes in place, only one TSC adjustment was observed for
each of the affected cpus with no failure.

Waiman Long (2):
  x86/tsc: Reduce external interference on max_warp detection
  x86/tsc_sync: Add synchronization overhead to tsc adjustment

 arch/x86/kernel/tsc_sync.c | 84 ++++++++++++++++++++++----------------
 1 file changed, 48 insertions(+), 36 deletions(-)

-- 
2.27.0