From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
This patch adds document for mediatek adsp mbox
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../bindings/mailbox/mtk,adsp-mbox.yaml | 52 +++++++++++++++++++
1 file changed, 52 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mailbox/mtk,adsp-mbox.yaml
diff --git a/Documentation/devicetree/bindings/mailbox/mtk,adsp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/mtk,adsp-mbox.yaml
new file mode 100644
index 000000000000..25756837797f
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/mtk,adsp-mbox.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mailbox/mtk,adsp-mbox.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek ADSP mailbox
+
+maintainers:
+ - Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
+
+description: |
+ The MTK ADSP mailbox Inter-Processor Communication (IPC) enables the SoC
+ to ommunicate with ADSP by passing messages through two mailbox channels.
+ The MTK ADSP mailbox IPC also provides the ability for one processor to
+ signal the other processor using interrupts.
+
+properties:
+ compatible:
+ items:
+ - const: mediatek,mt8195-adsp-mbox
+
+ "#mbox-cells":
+ const: 0
+
+ reg:
+ description:
+ Physical address base for dsp mbox registers.
+
+ interrupts:
+ description:
+ adsp mbox interrupt
+
+required:
+ - compatible
+ - "#mbox-cells"
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ adsp_mailbox0:mailbox@10816000 {
+ compatible = "mediatek,mt8195-adsp-mbox";
+ #mbox-cells = <0>;
+ reg = <0x10816000 0x1000>;
+ interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
--
2.18.0
On Thu, Feb 24, 2022 at 09:30:44PM +0800, Allen-KH Cheng wrote: > From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com> > > This patch adds document for mediatek adsp mbox > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > .../bindings/mailbox/mtk,adsp-mbox.yaml | 52 +++++++++++++++++++ > 1 file changed, 52 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mailbox/mtk,adsp-mbox.yaml > > diff --git a/Documentation/devicetree/bindings/mailbox/mtk,adsp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/mtk,adsp-mbox.yaml > new file mode 100644 > index 000000000000..25756837797f > --- /dev/null > +++ b/Documentation/devicetree/bindings/mailbox/mtk,adsp-mbox.yaml > @@ -0,0 +1,52 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mailbox/mtk,adsp-mbox.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Mediatek ADSP mailbox > + > +maintainers: > + - Allen-KH Cheng <Allen-KH.Cheng@mediatek.com> > + > +description: | > + The MTK ADSP mailbox Inter-Processor Communication (IPC) enables the SoC > + to ommunicate with ADSP by passing messages through two mailbox channels. > + The MTK ADSP mailbox IPC also provides the ability for one processor to > + signal the other processor using interrupts. > + > +properties: > + compatible: > + items: > + - const: mediatek,mt8195-adsp-mbox > + > + "#mbox-cells": > + const: 0 > + > + reg: > + description: > + Physical address base for dsp mbox registers. That's fairly obvious. Drop. You need to define how many: 'maxItems: 1' > + > + interrupts: > + description: > + adsp mbox interrupt Same here. > + > +required: > + - compatible > + - "#mbox-cells" > + - reg > + - interrupts > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + > + adsp_mailbox0:mailbox@10816000 { > + compatible = "mediatek,mt8195-adsp-mbox"; > + #mbox-cells = <0>; > + reg = <0x10816000 0x1000>; > + interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > -- > 2.18.0 > >
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