Add display nodes for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 115 +++++++++++++++++++++++
1 file changed, 115 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index e3314cdc7c1a..026f2d8141b0 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -32,6 +32,11 @@
i2c7 = &i2c7;
i2c8 = &i2c8;
i2c9 = &i2c9;
+ ovl0 = &ovl0;
+ ovl-2l0 = &ovl_2l0;
+ ovl-2l2 = &ovl_2l2;
+ rdma0 = &rdma0;
+ rdma4 = &rdma4;
};
clk26m: oscillator0 {
@@ -1224,6 +1229,13 @@
#clock-cells = <1>;
};
+ mutex: mutex@14001000 {
+ compatible = "mediatek,mt8192-disp-mutex";
+ reg = <0 0x14001000 0 0x1000>;
+ interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
+ };
+
smi_common: smi@14002000 {
compatible = "mediatek,mt8192-smi-common";
reg = <0 0x14002000 0 0x1000>;
@@ -1255,6 +1267,109 @@
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
};
+ ovl0: ovl@14005000 {
+ compatible = "mediatek,mt8192-disp-ovl";
+ reg = <0 0x14005000 0 0x1000>;
+ interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
+ <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ };
+
+ ovl_2l0: ovl@14006000 {
+ compatible = "mediatek,mt8192-disp-ovl-2l";
+ reg = <0 0x14006000 0 0x1000>;
+ interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+ iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
+ <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
+ };
+
+ rdma0: rdma@14007000 {
+ compatible = "mediatek,mt8192-disp-rdma";
+ reg = <0 0x14007000 0 0x1000>;
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+ iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
+ mediatek,larb = <&larb0>;
+ mediatek,rdma-fifo-size = <5120>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ };
+
+ color0: color@14009000 {
+ compatible = "mediatek,mt8192-disp-color",
+ "mediatek,mt8173-disp-color";
+ reg = <0 0x14009000 0 0x1000>;
+ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+ };
+
+ ccorr0: ccorr@1400a000 {
+ compatible = "mediatek,mt8192-disp-ccorr";
+ reg = <0 0x1400a000 0 0x1000>;
+ interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+ };
+
+ aal0: aal@1400b000 {
+ compatible = "mediatek,mt8192-disp-aal";
+ reg = <0 0x1400b000 0 0x1000>;
+ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_AAL0>;
+ };
+
+ gamma0: gamma@1400c000 {
+ compatible = "mediatek,mt8192-disp-gamma",
+ "mediatek,mt8183-disp-gamma";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+ };
+
+ postmask0: postmask@1400d000 {
+ compatible = "mediatek,mt8192-disp-postmask";
+ reg = <0 0x1400d000 0 0x1000>;
+ interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
+ iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
+ };
+
+ dither0: dither@1400e000 {
+ compatible = "mediatek,mt8192-disp-dither",
+ "mediatek,mt8183-disp-dither";
+ reg = <0 0x1400e000 0 0x1000>;
+ interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+ };
+
+ ovl_2l2: ovl@14014000 {
+ compatible = "mediatek,mt8192-disp-ovl-2l";
+ reg = <0 0x14014000 0 0x1000>;
+ interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
+ iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
+ <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
+ };
+
+ rdma4: rdma@14015000 {
+ compatible = "mediatek,mt8192-disp-rdma";
+ reg = <0 0x14015000 0 0x1000>;
+ interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA4>;
+ iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
+ mediatek,rdma-fifo-size = <2048>;
+ };
+
dpi0: dpi@14016000 {
compatible = "mediatek,mt8192-dpi";
reg = <0 0x14016000 0 0x1000>;
--
2.18.0
Hi, On Fri, Feb 18, 2022 at 5:16 PM Allen-KH Cheng <allen-kh.cheng@mediatek.com> wrote: > > Add display nodes for mt8192 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 115 +++++++++++++++++++++++ > 1 file changed, 115 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index e3314cdc7c1a..026f2d8141b0 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -32,6 +32,11 @@ > i2c7 = &i2c7; > i2c8 = &i2c8; > i2c9 = &i2c9; > + ovl0 = &ovl0; > + ovl-2l0 = &ovl_2l0; > + ovl-2l2 = &ovl_2l2; > + rdma0 = &rdma0; > + rdma4 = &rdma4; > }; > > clk26m: oscillator0 { > @@ -1224,6 +1229,13 @@ > #clock-cells = <1>; > }; > > + mutex: mutex@14001000 { > + compatible = "mediatek,mt8192-disp-mutex"; > + reg = <0 0x14001000 0 0x1000>; > + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&mmsys CLK_MM_DISP_MUTEX0>; > + }; > + > smi_common: smi@14002000 { > compatible = "mediatek,mt8192-smi-common"; > reg = <0 0x14002000 0 0x1000>; > @@ -1255,6 +1267,109 @@ > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > }; > > + ovl0: ovl@14005000 { > + compatible = "mediatek,mt8192-disp-ovl"; > + reg = <0 0x14005000 0 0x1000>; > + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&mmsys CLK_MM_DISP_OVL0>; > + iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, > + <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + }; > + > + ovl_2l0: ovl@14006000 { > + compatible = "mediatek,mt8192-disp-ovl-2l"; > + reg = <0 0x14006000 0 0x1000>; > + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; > + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, > + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; > + }; > + > + rdma0: rdma@14007000 { > + compatible = "mediatek,mt8192-disp-rdma"; > + reg = <0 0x14007000 0 0x1000>; > + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&mmsys CLK_MM_DISP_RDMA0>; > + iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>; > + mediatek,larb = <&larb0>; > + mediatek,rdma-fifo-size = <5120>; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + }; > + > + color0: color@14009000 { > + compatible = "mediatek,mt8192-disp-color", > + "mediatek,mt8173-disp-color"; > + reg = <0 0x14009000 0 0x1000>; > + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_COLOR0>; > + }; > + > + ccorr0: ccorr@1400a000 { > + compatible = "mediatek,mt8192-disp-ccorr"; > + reg = <0 0x1400a000 0 0x1000>; > + interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_CCORR0>; > + }; > + > + aal0: aal@1400b000 { > + compatible = "mediatek,mt8192-disp-aal"; git.kernel.org/chunkuang.hu/c/4ed545e7d10049b5492afc184e61a67e478a2cfd suggests that there should be a fallback compatible? Otherwise this doesn't probe. ChenYu
On Tue, Feb 22, 2022 at 06:24:29PM +0800, Chen-Yu Tsai wrote: > Hi, > > On Fri, Feb 18, 2022 at 5:16 PM Allen-KH Cheng > <allen-kh.cheng@mediatek.com> wrote: > > > > Add display nodes for mt8192 SoC. > > > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > > --- > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 115 +++++++++++++++++++++++ > > 1 file changed, 115 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > index e3314cdc7c1a..026f2d8141b0 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > @@ -32,6 +32,11 @@ > > i2c7 = &i2c7; > > i2c8 = &i2c8; > > i2c9 = &i2c9; > > + ovl0 = &ovl0; > > + ovl-2l0 = &ovl_2l0; > > + ovl-2l2 = &ovl_2l2; > > + rdma0 = &rdma0; > > + rdma4 = &rdma4; > > }; > > > > clk26m: oscillator0 { > > @@ -1224,6 +1229,13 @@ > > #clock-cells = <1>; > > }; > > > > + mutex: mutex@14001000 { > > + compatible = "mediatek,mt8192-disp-mutex"; > > + reg = <0 0x14001000 0 0x1000>; > > + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>; > > + clocks = <&mmsys CLK_MM_DISP_MUTEX0>; > > + }; > > + > > smi_common: smi@14002000 { > > compatible = "mediatek,mt8192-smi-common"; > > reg = <0 0x14002000 0 0x1000>; > > @@ -1255,6 +1267,109 @@ > > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > > }; > > > > + ovl0: ovl@14005000 { > > + compatible = "mediatek,mt8192-disp-ovl"; > > + reg = <0 0x14005000 0 0x1000>; > > + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; > > + clocks = <&mmsys CLK_MM_DISP_OVL0>; > > + iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, > > + <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; > > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > > + }; > > + > > + ovl_2l0: ovl@14006000 { > > + compatible = "mediatek,mt8192-disp-ovl-2l"; > > + reg = <0 0x14006000 0 0x1000>; > > + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>; > > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > > + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; > > + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, > > + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; > > + }; > > + > > + rdma0: rdma@14007000 { > > + compatible = "mediatek,mt8192-disp-rdma"; > > + reg = <0 0x14007000 0 0x1000>; > > + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>; > > + clocks = <&mmsys CLK_MM_DISP_RDMA0>; > > + iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>; > > + mediatek,larb = <&larb0>; > > + mediatek,rdma-fifo-size = <5120>; > > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > > + }; > > + > > + color0: color@14009000 { > > + compatible = "mediatek,mt8192-disp-color", > > + "mediatek,mt8173-disp-color"; > > + reg = <0 0x14009000 0 0x1000>; > > + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>; > > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > > + clocks = <&mmsys CLK_MM_DISP_COLOR0>; > > + }; > > + > > + ccorr0: ccorr@1400a000 { > > + compatible = "mediatek,mt8192-disp-ccorr"; > > + reg = <0 0x1400a000 0 0x1000>; > > + interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; > > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > > + clocks = <&mmsys CLK_MM_DISP_CCORR0>; > > + }; > > + > > + aal0: aal@1400b000 { > > + compatible = "mediatek,mt8192-disp-aal"; > > git.kernel.org/chunkuang.hu/c/4ed545e7d10049b5492afc184e61a67e478a2cfd > > suggests that there should be a fallback compatible? Otherwise this > doesn't probe. Indeed, the "mediatek,mt8173-disp-aal" compatible should be appended here for the node to probe. Thanks, Nícolas
Il 18/02/22 10:16, Allen-KH Cheng ha scritto: > Add display nodes for mt8192 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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