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[PATCH net-next v2 3/9] net: ethernet: mtk-star-emac: add support for MT8365 SoC

Biao Huang posted 9 patches 4 years ago
There is a newer version of this series
[PATCH net-next v2 3/9] net: ethernet: mtk-star-emac: add support for MT8365 SoC
Posted by Biao Huang 4 years ago 
Add Ethernet driver support for MT8365 SoC.

Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Signed-off-by: Yinghua Pan <ot_yinghua.pan@mediatek.com>
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 drivers/net/ethernet/mediatek/mtk_star_emac.c | 75 ++++++++++++++++---
 1 file changed, 64 insertions(+), 11 deletions(-)

diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/ethernet/mediatek/mtk_star_emac.c
index a8fbbbcd185b..a3884beaa3fe 100644
--- a/drivers/net/ethernet/mediatek/mtk_star_emac.c
+++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c
@@ -151,6 +151,7 @@ static const char *const mtk_star_clk_names[] = { "core", "reg", "trans" };
 #define MTK_STAR_REG_MAC_CLK_CONF		0x00ac
 #define MTK_STAR_MSK_MAC_CLK_CONF		GENMASK(7, 0)
 #define MTK_STAR_BIT_CLK_DIV_10			0x0a
+#define MTK_STAR_BIT_CLK_DIV_50			0x32
 
 /* Counter registers. */
 #define MTK_STAR_REG_C_RXOKPKT			0x0100
@@ -183,9 +184,11 @@ static const char *const mtk_star_clk_names[] = { "core", "reg", "trans" };
 #define MTK_STAR_REG_C_RX_TWIST			0x0218
 
 /* Ethernet CFG Control */
-#define MTK_PERICFG_REG_NIC_CFG_CON		0x03c4
-#define MTK_PERICFG_MSK_NIC_CFG_CON_CFG_MII	GENMASK(3, 0)
-#define MTK_PERICFG_BIT_NIC_CFG_CON_RMII	BIT(0)
+#define MTK_PERICFG_REG_NIC_CFG0_CON		0x03c4
+#define MTK_PERICFG_REG_NIC_CFG1_CON		0x03c8
+#define MTK_PERICFG_REG_NIC_CFG_CON_V2		0x0c10
+#define MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF	GENMASK(3, 0)
+#define MTK_PERICFG_BIT_NIC_CFG_CON_RMII	1
 
 /* Represents the actual structure of descriptors used by the MAC. We can
  * reuse the same structure for both TX and RX - the layout is the same, only
@@ -234,6 +237,7 @@ struct mtk_star_ring {
 };
 
 struct mtk_star_compat {
+	int (*set_interface_mode)(struct net_device *ndev);
 	unsigned char bit_clk_div;
 };
 
@@ -909,13 +913,6 @@ static void mtk_star_init_config(struct mtk_star_priv *priv)
 			   priv->compat_data->bit_clk_div);
 }
 
-static void mtk_star_set_mode_rmii(struct mtk_star_priv *priv)
-{
-	regmap_update_bits(priv->pericfg, MTK_PERICFG_REG_NIC_CFG_CON,
-			   MTK_PERICFG_MSK_NIC_CFG_CON_CFG_MII,
-			   MTK_PERICFG_BIT_NIC_CFG_CON_RMII);
-}
-
 static int mtk_star_enable(struct net_device *ndev)
 {
 	struct mtk_star_priv *priv = netdev_priv(ndev);
@@ -1531,7 +1528,13 @@ static int mtk_star_probe(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
-	mtk_star_set_mode_rmii(priv);
+	if (priv->compat_data->set_interface_mode) {
+		ret = priv->compat_data->set_interface_mode(ndev);
+		if (ret) {
+			dev_err(dev, "Failed to set phy interface, err = %d\n", ret);
+			return -EINVAL;
+		}
+	}
 
 	ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
 	if (ret) {
@@ -1564,10 +1567,58 @@ static int mtk_star_probe(struct platform_device *pdev)
 	return devm_register_netdev(dev, ndev);
 }
 
+static int mt8516_set_interface_mode(struct net_device *ndev)
+{
+	struct mtk_star_priv *priv = netdev_priv(ndev);
+	struct device *dev = mtk_star_get_dev(priv);
+	unsigned int intf_val;
+
+	switch (priv->phy_intf) {
+	case PHY_INTERFACE_MODE_RMII:
+		intf_val = MTK_PERICFG_BIT_NIC_CFG_CON_RMII;
+		break;
+	default:
+		dev_err(dev, "This interface not supported\n");
+		return -EINVAL;
+	}
+
+	return regmap_update_bits(priv->pericfg,
+				  MTK_PERICFG_REG_NIC_CFG0_CON,
+				  MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF,
+				  intf_val);
+}
+
+static int mt8365_set_interface_mode(struct net_device *ndev)
+{
+	struct mtk_star_priv *priv = netdev_priv(ndev);
+	struct device *dev = mtk_star_get_dev(priv);
+	unsigned int intf_val;
+
+	switch (priv->phy_intf) {
+	case PHY_INTERFACE_MODE_RMII:
+		intf_val = MTK_PERICFG_BIT_NIC_CFG_CON_RMII;
+		break;
+	default:
+		dev_err(dev, "This interface not supported\n");
+		return -EINVAL;
+	}
+
+	return regmap_update_bits(priv->pericfg,
+				  MTK_PERICFG_REG_NIC_CFG_CON_V2,
+				  MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF,
+				  intf_val);
+}
+
 static const struct mtk_star_compat mtk_star_mt8516_compat = {
+	.set_interface_mode = mt8516_set_interface_mode,
 	.bit_clk_div = MTK_STAR_BIT_CLK_DIV_10,
 };
 
+static const struct mtk_star_compat mtk_star_mt8365_compat = {
+	.set_interface_mode = mt8365_set_interface_mode,
+	.bit_clk_div = MTK_STAR_BIT_CLK_DIV_50,
+};
+
 static const struct of_device_id mtk_star_of_match[] = {
 	{ .compatible = "mediatek,mt8516-eth",
 	  .data = &mtk_star_mt8516_compat },
@@ -1575,6 +1626,8 @@ static const struct of_device_id mtk_star_of_match[] = {
 	  .data = &mtk_star_mt8516_compat },
 	{ .compatible = "mediatek,mt8175-eth",
 	  .data = &mtk_star_mt8516_compat },
+	{ .compatible = "mediatek,mt8365-eth",
+	  .data = &mtk_star_mt8365_compat },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, mtk_star_of_match);
-- 
2.25.1
Re: [PATCH net-next v2 3/9] net: ethernet: mtk-star-emac: add support for MT8365 SoC
Posted by Macpaul Lin 4 years ago 
On 1/27/22 9:58 AM, Biao Huang wrote:
> Add Ethernet driver support for MT8365 SoC.
> 
> Signed-off-by: Biao Huang <biao.huang@mediatek.com>
> Signed-off-by: Yinghua Pan <ot_yinghua.pan@mediatek.com>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>   drivers/net/ethernet/mediatek/mtk_star_emac.c | 75 ++++++++++++++++---
>   1 file changed, 64 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/ethernet/mediatek/mtk_star_emac.c
> index a8fbbbcd185b..a3884beaa3fe 100644
> --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c
> +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c
> @@ -151,6 +151,7 @@ static const char *const mtk_star_clk_names[] = { "core", "reg", "trans" };
>   #define MTK_STAR_REG_MAC_CLK_CONF		0x00ac
>   #define MTK_STAR_MSK_MAC_CLK_CONF		GENMASK(7, 0)
>   #define MTK_STAR_BIT_CLK_DIV_10			0x0a
> +#define MTK_STAR_BIT_CLK_DIV_50			0x32
>   
>   /* Counter registers. */
>   #define MTK_STAR_REG_C_RXOKPKT			0x0100
> @@ -183,9 +184,11 @@ static const char *const mtk_star_clk_names[] = { "core", "reg", "trans" };
>   #define MTK_STAR_REG_C_RX_TWIST			0x0218
>   
>   /* Ethernet CFG Control */
> -#define MTK_PERICFG_REG_NIC_CFG_CON		0x03c4
> -#define MTK_PERICFG_MSK_NIC_CFG_CON_CFG_MII	GENMASK(3, 0)
> -#define MTK_PERICFG_BIT_NIC_CFG_CON_RMII	BIT(0)
> +#define MTK_PERICFG_REG_NIC_CFG0_CON		0x03c4
> +#define MTK_PERICFG_REG_NIC_CFG1_CON		0x03c8
> +#define MTK_PERICFG_REG_NIC_CFG_CON_V2		0x0c10
> +#define MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF	GENMASK(3, 0)
> +#define MTK_PERICFG_BIT_NIC_CFG_CON_RMII	1
>   
>   /* Represents the actual structure of descriptors used by the MAC. We can
>    * reuse the same structure for both TX and RX - the layout is the same, only
> @@ -234,6 +237,7 @@ struct mtk_star_ring {
>   };
>   
>   struct mtk_star_compat {
> +	int (*set_interface_mode)(struct net_device *ndev);
>   	unsigned char bit_clk_div;
>   };
>   
> @@ -909,13 +913,6 @@ static void mtk_star_init_config(struct mtk_star_priv *priv)
>   			   priv->compat_data->bit_clk_div);
>   }
>   
> -static void mtk_star_set_mode_rmii(struct mtk_star_priv *priv)
> -{
> -	regmap_update_bits(priv->pericfg, MTK_PERICFG_REG_NIC_CFG_CON,
> -			   MTK_PERICFG_MSK_NIC_CFG_CON_CFG_MII,
> -			   MTK_PERICFG_BIT_NIC_CFG_CON_RMII);
> -}
> -
>   static int mtk_star_enable(struct net_device *ndev)
>   {
>   	struct mtk_star_priv *priv = netdev_priv(ndev);
> @@ -1531,7 +1528,13 @@ static int mtk_star_probe(struct platform_device *pdev)
>   		return -ENODEV;
>   	}
>   
> -	mtk_star_set_mode_rmii(priv);
> +	if (priv->compat_data->set_interface_mode) {
> +		ret = priv->compat_data->set_interface_mode(ndev);
> +		if (ret) {
> +			dev_err(dev, "Failed to set phy interface, err = %d\n", ret);
> +			return -EINVAL;
> +		}
> +	}
>   
>   	ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
>   	if (ret) {
> @@ -1564,10 +1567,58 @@ static int mtk_star_probe(struct platform_device *pdev)
>   	return devm_register_netdev(dev, ndev);
>   }
>   
> +static int mt8516_set_interface_mode(struct net_device *ndev)
> +{
> +	struct mtk_star_priv *priv = netdev_priv(ndev);
> +	struct device *dev = mtk_star_get_dev(priv);
> +	unsigned int intf_val;
> +
> +	switch (priv->phy_intf) {
> +	case PHY_INTERFACE_MODE_RMII:
> +		intf_val = MTK_PERICFG_BIT_NIC_CFG_CON_RMII;
> +		break;
> +	default:
> +		dev_err(dev, "This interface not supported\n");
> +		return -EINVAL;
> +	}
> +
> +	return regmap_update_bits(priv->pericfg,
> +				  MTK_PERICFG_REG_NIC_CFG0_CON,
> +				  MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF,
> +				  intf_val);
> +}
> +
> +static int mt8365_set_interface_mode(struct net_device *ndev)
> +{
> +	struct mtk_star_priv *priv = netdev_priv(ndev);
> +	struct device *dev = mtk_star_get_dev(priv);
> +	unsigned int intf_val;
> +
> +	switch (priv->phy_intf) {
> +	case PHY_INTERFACE_MODE_RMII:
> +		intf_val = MTK_PERICFG_BIT_NIC_CFG_CON_RMII;
> +		break;
> +	default:
> +		dev_err(dev, "This interface not supported\n");
> +		return -EINVAL;
> +	}
> +
> +	return regmap_update_bits(priv->pericfg,
> +				  MTK_PERICFG_REG_NIC_CFG_CON_V2,
> +				  MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF,
> +				  intf_val);
> +}
> +
>   static const struct mtk_star_compat mtk_star_mt8516_compat = {
> +	.set_interface_mode = mt8516_set_interface_mode,
>   	.bit_clk_div = MTK_STAR_BIT_CLK_DIV_10,
>   };
>   
> +static const struct mtk_star_compat mtk_star_mt8365_compat = {
> +	.set_interface_mode = mt8365_set_interface_mode,
> +	.bit_clk_div = MTK_STAR_BIT_CLK_DIV_50,
> +};
> +
>   static const struct of_device_id mtk_star_of_match[] = {
>   	{ .compatible = "mediatek,mt8516-eth",
>   	  .data = &mtk_star_mt8516_compat },
> @@ -1575,6 +1626,8 @@ static const struct of_device_id mtk_star_of_match[] = {
>   	  .data = &mtk_star_mt8516_compat },
>   	{ .compatible = "mediatek,mt8175-eth",
>   	  .data = &mtk_star_mt8516_compat },
> +	{ .compatible = "mediatek,mt8365-eth",
> +	  .data = &mtk_star_mt8365_compat },
>   	{ }
>   };
>   MODULE_DEVICE_TABLE(of, mtk_star_of_match);
> 

Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com>

Regards,
Macpaul Lin

Patchew 2.1-devel-b67e4c2

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