Add clocks for MLP modules on Renesas R-Car E3 and D3 SoCs.

Similar to other R-Car Gen3 SoC, exact information on parent for MLP
clock on E3 and D3 is not available. However, since parent for this
clocl is not anyhow software-controllable, the only harm from this
is inexact information exported via debugfs. So just keep the parent
set in the same way as with other Gen3 SoCs.

Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
---
 drivers/clk/renesas/r8a77990-cpg-mssr.c | 1 +
 drivers/clk/renesas/r8a77995-cpg-mssr.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
index a582f2ec3294..aaa4eaab9cc3 100644
--- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -197,6 +197,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
 	DEF_MOD("du0",			 724,	R8A77990_CLK_S1D1),
 	DEF_MOD("lvds",			 727,	R8A77990_CLK_S2D1),
 
+	DEF_MOD("mlp",			 802,	R8A77990_CLK_S2D1),
 	DEF_MOD("vin5",			 806,	R8A77990_CLK_S1D2),
 	DEF_MOD("vin4",			 807,	R8A77990_CLK_S1D2),
 	DEF_MOD("etheravb",		 812,	R8A77990_CLK_S3D2),
diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c
index 81c0bc1e78af..480c130d2b1b 100644
--- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
@@ -159,6 +159,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
 	DEF_MOD("du1",			 723,	R8A77995_CLK_S1D1),
 	DEF_MOD("du0",			 724,	R8A77995_CLK_S1D1),
 	DEF_MOD("lvds",			 727,	R8A77995_CLK_S2D1),
+	DEF_MOD("mlp",			 802,	R8A77995_CLK_S2D1),
 	DEF_MOD("vin4",			 807,	R8A77995_CLK_S1D2),
 	DEF_MOD("etheravb",		 812,	R8A77995_CLK_S3D2),
 	DEF_MOD("imr0",			 823,	R8A77995_CLK_S1D2),
-- 
2.30.2

On 25.12.2021 22:39, Nikita Yushchenko wrote:

> Add clocks for MLP modules on Renesas R-Car E3 and D3 SoCs.
> 
> Similar to other R-Car Gen3 SoC, exact information on parent for MLP
> clock on E3 and D3 is not available. However, since parent for this
> clocl is not anyhow software-controllable, the only harm from this

    s/clocl/clock/. :-)

> is inexact information exported via debugfs. So just keep the parent
> set in the same way as with other Gen3 SoCs.
> 
> Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
[...]

MBR, Sergey

On Sun, Dec 26, 2021 at 6:46 PM Sergei Shtylyov
<sergei.shtylyov@gmail.com> wrote:
> On 25.12.2021 22:39, Nikita Yushchenko wrote:
> > Add clocks for MLP modules on Renesas R-Car E3 and D3 SoCs.
> >
> > Similar to other R-Car Gen3 SoC, exact information on parent for MLP
> > clock on E3 and D3 is not available. However, since parent for this
> > clocl is not anyhow software-controllable, the only harm from this
>
>     s/clocl/clock/. :-)
>
> > is inexact information exported via debugfs. So just keep the parent
> > set in the same way as with other Gen3 SoCs.
> >
> > Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v5.18, with the typos fixed.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds