Adds decoder dt-bindings for mt8192.
Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
---
.../media/mediatek,vcodec-subdev-decoder.yaml | 266 ++++++++++++++++++
1 file changed, 266 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
new file mode 100644
index 000000000000..67cbcf8b3373
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
@@ -0,0 +1,266 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Mediatek Video Decode Accelerator With Multi Hardware
+
+maintainers:
+ - Yunfei Dong <yunfei.dong@mediatek.com>
+
+description: |
+ Mediatek Video Decode is the video decode hardware present in Mediatek
+ SoCs which supports high resolution decoding functionalities. Required
+ parent and child device node.
+
+ About the Decoder Hardware Block Diagram, please check below:
+
+ +---------------------------------+------------------------------------+
+ | | |
+ | input -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output |
+ | || | || |
+ +------------||-------------------+---------------------||-------------+
+ lat workqueue | core workqueue <parent>
+ -------------||-----------------------------------------||------------------
+ || || <child>
+ \/ <----------------HW index-------------->\/
+ +------------------------------------------------------+
+ | enable/disable |
+ | clk power irq iommu |
+ | (lat/lat soc/core0/core1) |
+ +------------------------------------------------------+
+
+ As above, there are parent and child devices, child mean each hardware. The child device
+ controls the information of each hardware independent which include clk/power/irq.
+
+ There are two workqueues in parent device: lat workqueue and core workqueue. They are used
+ to lat and core hardware deocder. Lat workqueue need to get input bitstream and lat buffer,
+ then enable lat to decode, writing the result to lat buffer, dislabe hardware when lat decode
+ done. Core workqueue need to get lat buffer and output buffer, then enable core to decode,
+ writing the result to output buffer, disable hardware when core decode done. These two
+ hardwares will decode each frame cyclically.
+
+ For the smi common may not the same for each hardware, can't combine all hardware in one node,
+ or leading to iommu fault when access dram data.
+
+properties:
+ compatible:
+ const: mediatek,mt8192-vcodec-dec
+
+ reg:
+ maxItems: 1
+
+ iommus:
+ minItems: 1
+ maxItems: 32
+ description: |
+ List of the hardware port in respective IOMMU block for current Socs.
+ Refer to bindings/iommu/mediatek,iommu.yaml.
+
+ mediatek,scp:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ maxItems: 1
+ description: |
+ The node of system control processor (SCP), using
+ the remoteproc & rpmsg framework.
+ $ref: /schemas/remoteproc/mtk,scp.yaml
+
+ dma-ranges:
+ maxItems: 1
+ description: |
+ Describes the physical address space of IOMMU maps to memory.
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ ranges: true
+
+# Required child node:
+patternProperties:
+ vcodec-lat:
+ type: object
+
+ properties:
+ compatible:
+ const: mediatek,mtk-vcodec-lat
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ iommus:
+ minItems: 1
+ maxItems: 32
+ description: |
+ List of the hardware port in respective IOMMU block for current Socs.
+ Refer to bindings/iommu/mediatek,iommu.yaml.
+
+ clocks:
+ maxItems: 5
+
+ clock-names:
+ items:
+ - const: sel
+ - const: soc-vdec
+ - const: soc-lat
+ - const: vdec
+ - const: top
+
+ assigned-clocks:
+ maxItems: 1
+
+ assigned-clock-parents:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ required:
+ - compatible
+ - reg
+ - interrupts
+ - iommus
+ - clocks
+ - clock-names
+ - assigned-clocks
+ - assigned-clock-parents
+ - power-domains
+
+ additionalProperties: false
+
+ vcodec-core:
+ type: object
+
+ properties:
+ compatible:
+ const: mediatek,mtk-vcodec-core
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ iommus:
+ minItems: 1
+ maxItems: 32
+ description: |
+ List of the hardware port in respective IOMMU block for current Socs.
+ Refer to bindings/iommu/mediatek,iommu.yaml.
+
+ clocks:
+ maxItems: 5
+
+ clock-names:
+ items:
+ - const: sel
+ - const: soc-vdec
+ - const: soc-lat
+ - const: vdec
+ - const: top
+
+ assigned-clocks:
+ maxItems: 1
+
+ assigned-clock-parents:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ required:
+ - compatible
+ - reg
+ - interrupts
+ - iommus
+ - clocks
+ - clock-names
+ - assigned-clocks
+ - assigned-clock-parents
+ - power-domains
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - iommus
+ - mediatek,scp
+ - dma-ranges
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/memory/mt8192-larb-port.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/clock/mt8192-clk.h>
+ #include <dt-bindings/power/mt8192-power.h>
+
+ video-codec@16000000 {
+ compatible = "mediatek,mt8192-vcodec-dec";
+ mediatek,scp = <&scp>;
+ iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
+ dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x16000000 0x40000>;
+ reg = <0x16000000 0x1000>; /* VDEC_SYS */
+ vcodec-lat@10000 {
+ compatible = "mediatek,mtk-vcodec-lat";
+ reg = <0x10000 0x800>;
+ interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
+ clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+ <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
+ <&vdecsys_soc CLK_VDEC_SOC_LAT>,
+ <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
+ <&topckgen CLK_TOP_MAINPLL_D4>;
+ clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
+ assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
+ };
+
+ vcodec-core@25000 {
+ compatible = "mediatek,mtk-vcodec-core";
+ reg = <0x25000 0x1000>;
+ interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
+ clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+ <&vdecsys CLK_VDEC_VDEC>,
+ <&vdecsys CLK_VDEC_LAT>,
+ <&vdecsys CLK_VDEC_LARB1>,
+ <&topckgen CLK_TOP_MAINPLL_D4>;
+ clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
+ assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
+ };
+ };
--
2.25.1
Reviewed-by: Steve Cho <stevecho@chromium.org>
On Wed, Dec 1, 2021 at 7:46 PM Yunfei Dong <yunfei.dong@mediatek.com> wrote:
>
> Adds decoder dt-bindings for mt8192.
basic question: what is dt-bindings?
Is this yaml file supposed to be used for some settings?
>
> Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
> ---
> .../media/mediatek,vcodec-subdev-decoder.yaml | 266 ++++++++++++++++++
> 1 file changed, 266 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
>
> diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
> new file mode 100644
> index 000000000000..67cbcf8b3373
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
> @@ -0,0 +1,266 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Mediatek Video Decode Accelerator With Multi Hardware
Is Multi Hardware supposed to mean parent & child devices in this context?
> +
> +maintainers:
> + - Yunfei Dong <yunfei.dong@mediatek.com>
> +
> +description: |
> + Mediatek Video Decode is the video decode hardware present in Mediatek
> + SoCs which supports high resolution decoding functionalities. Required
> + parent and child device node.
> +
> + About the Decoder Hardware Block Diagram, please check below:
Great to see this diagram and description!
> +
> + +---------------------------------+------------------------------------+
> + | | |
> + | input -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output |
> + | || | || |
> + +------------||-------------------+---------------------||-------------+
> + lat workqueue | core workqueue <parent>
> + -------------||-----------------------------------------||------------------
> + || || <child>
> + \/ <----------------HW index-------------->\/
> + +------------------------------------------------------+
> + | enable/disable |
> + | clk power irq iommu |
> + | (lat/lat soc/core0/core1) |
> + +------------------------------------------------------+
> +
> + As above, there are parent and child devices, child mean each hardware. The child device
> + controls the information of each hardware independent which include clk/power/irq.
> +
> + There are two workqueues in parent device: lat workqueue and core workqueue. They are used
> + to lat and core hardware deocder. Lat workqueue need to get input bitstream and lat buffer,
> + then enable lat to decode, writing the result to lat buffer, dislabe hardware when lat decode
> + done. Core workqueue need to get lat buffer and output buffer, then enable core to decode,
> + writing the result to output buffer, disable hardware when core decode done. These two
> + hardwares will decode each frame cyclically.
> +
> + For the smi common may not the same for each hardware, can't combine all hardware in one node,
> + or leading to iommu fault when access dram data.
> +
> +properties:
> + compatible:
> + const: mediatek,mt8192-vcodec-dec
> +
> + reg:
> + maxItems: 1
> +
> + iommus:
> + minItems: 1
> + maxItems: 32
> + description: |
> + List of the hardware port in respective IOMMU block for current Socs.
> + Refer to bindings/iommu/mediatek,iommu.yaml.
> +
> + mediatek,scp:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + maxItems: 1
> + description: |
> + The node of system control processor (SCP), using
> + the remoteproc & rpmsg framework.
> + $ref: /schemas/remoteproc/mtk,scp.yaml
> +
> + dma-ranges:
> + maxItems: 1
> + description: |
> + Describes the physical address space of IOMMU maps to memory.
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 1
> +
> + ranges: true
> +
> +# Required child node:
> +patternProperties:
> + vcodec-lat:
> + type: object
> +
> + properties:
> + compatible:
> + const: mediatek,mtk-vcodec-lat
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + iommus:
> + minItems: 1
> + maxItems: 32
> + description: |
> + List of the hardware port in respective IOMMU block for current Socs.
> + Refer to bindings/iommu/mediatek,iommu.yaml.
> +
> + clocks:
> + maxItems: 5
> +
> + clock-names:
> + items:
> + - const: sel
> + - const: soc-vdec
> + - const: soc-lat
> + - const: vdec
> + - const: top
> +
> + assigned-clocks:
> + maxItems: 1
> +
> + assigned-clock-parents:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + required:
> + - compatible
> + - reg
> + - interrupts
> + - iommus
> + - clocks
> + - clock-names
> + - assigned-clocks
> + - assigned-clock-parents
> + - power-domains
> +
> + additionalProperties: false
> +
> + vcodec-core:
> + type: object
> +
> + properties:
> + compatible:
> + const: mediatek,mtk-vcodec-core
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + iommus:
> + minItems: 1
> + maxItems: 32
> + description: |
> + List of the hardware port in respective IOMMU block for current Socs.
> + Refer to bindings/iommu/mediatek,iommu.yaml.
> +
> + clocks:
> + maxItems: 5
> +
> + clock-names:
> + items:
> + - const: sel
> + - const: soc-vdec
> + - const: soc-lat
> + - const: vdec
> + - const: top
> +
> + assigned-clocks:
> + maxItems: 1
> +
> + assigned-clock-parents:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + required:
> + - compatible
> + - reg
> + - interrupts
> + - iommus
> + - clocks
> + - clock-names
> + - assigned-clocks
> + - assigned-clock-parents
> + - power-domains
> +
> + additionalProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - iommus
> + - mediatek,scp
> + - dma-ranges
> + - ranges
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/memory/mt8192-larb-port.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/clock/mt8192-clk.h>
> + #include <dt-bindings/power/mt8192-power.h>
> +
> + video-codec@16000000 {
> + compatible = "mediatek,mt8192-vcodec-dec";
> + mediatek,scp = <&scp>;
> + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x16000000 0x40000>;
> + reg = <0x16000000 0x1000>; /* VDEC_SYS */
> + vcodec-lat@10000 {
> + compatible = "mediatek,mtk-vcodec-lat";
> + reg = <0x10000 0x800>;
> + interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> + <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
> + <&vdecsys_soc CLK_VDEC_SOC_LAT>,
> + <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
> + <&topckgen CLK_TOP_MAINPLL_D4>;
> + clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
> + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
> + };
> +
> + vcodec-core@25000 {
> + compatible = "mediatek,mtk-vcodec-core";
> + reg = <0x25000 0x1000>;
> + interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
> + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> + <&vdecsys CLK_VDEC_VDEC>,
> + <&vdecsys CLK_VDEC_LAT>,
> + <&vdecsys CLK_VDEC_LARB1>,
> + <&topckgen CLK_TOP_MAINPLL_D4>;
> + clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
> + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
> + };
> + };
> --
> 2.25.1
>
On Thu, Dec 02, 2021 at 11:45:40AM +0800, Yunfei Dong wrote:
> Adds decoder dt-bindings for mt8192.
>
> Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
> ---
> .../media/mediatek,vcodec-subdev-decoder.yaml | 266 ++++++++++++++++++
> 1 file changed, 266 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
>
> diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
> new file mode 100644
> index 000000000000..67cbcf8b3373
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
> @@ -0,0 +1,266 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Mediatek Video Decode Accelerator With Multi Hardware
> +
> +maintainers:
> + - Yunfei Dong <yunfei.dong@mediatek.com>
> +
> +description: |
> + Mediatek Video Decode is the video decode hardware present in Mediatek
> + SoCs which supports high resolution decoding functionalities. Required
> + parent and child device node.
> +
> + About the Decoder Hardware Block Diagram, please check below:
> +
> + +---------------------------------+------------------------------------+
> + | | |
> + | input -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output |
> + | || | || |
> + +------------||-------------------+---------------------||-------------+
> + lat workqueue | core workqueue <parent>
> + -------------||-----------------------------------------||------------------
> + || || <child>
> + \/ <----------------HW index-------------->\/
> + +------------------------------------------------------+
> + | enable/disable |
> + | clk power irq iommu |
> + | (lat/lat soc/core0/core1) |
> + +------------------------------------------------------+
> +
> + As above, there are parent and child devices, child mean each hardware. The child device
> + controls the information of each hardware independent which include clk/power/irq.
> +
> + There are two workqueues in parent device: lat workqueue and core workqueue. They are used
> + to lat and core hardware deocder. Lat workqueue need to get input bitstream and lat buffer,
> + then enable lat to decode, writing the result to lat buffer, dislabe hardware when lat decode
> + done. Core workqueue need to get lat buffer and output buffer, then enable core to decode,
> + writing the result to output buffer, disable hardware when core decode done. These two
> + hardwares will decode each frame cyclically.
> +
> + For the smi common may not the same for each hardware, can't combine all hardware in one node,
> + or leading to iommu fault when access dram data.
> +
> +properties:
> + compatible:
> + const: mediatek,mt8192-vcodec-dec
> +
> + reg:
> + maxItems: 1
> +
> + iommus:
> + minItems: 1
> + maxItems: 32
> + description: |
> + List of the hardware port in respective IOMMU block for current Socs.
> + Refer to bindings/iommu/mediatek,iommu.yaml.
> +
> + mediatek,scp:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + maxItems: 1
> + description: |
> + The node of system control processor (SCP), using
> + the remoteproc & rpmsg framework.
> + $ref: /schemas/remoteproc/mtk,scp.yaml
'$ref' is not valid here. Just 'See remoteproc/mtk,scp.yaml'
> +
> + dma-ranges:
> + maxItems: 1
> + description: |
> + Describes the physical address space of IOMMU maps to memory.
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 1
> +
> + ranges: true
> +
> +# Required child node:
> +patternProperties:
> + vcodec-lat:
'^vcodec-lat@[0-9a-f]+$':
> + type: object
> +
> + properties:
> + compatible:
> + const: mediatek,mtk-vcodec-lat
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + iommus:
> + minItems: 1
> + maxItems: 32
> + description: |
> + List of the hardware port in respective IOMMU block for current Socs.
> + Refer to bindings/iommu/mediatek,iommu.yaml.
> +
> + clocks:
> + maxItems: 5
> +
> + clock-names:
> + items:
> + - const: sel
> + - const: soc-vdec
> + - const: soc-lat
> + - const: vdec
> + - const: top
> +
> + assigned-clocks:
> + maxItems: 1
> +
> + assigned-clock-parents:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + required:
> + - compatible
> + - reg
> + - interrupts
> + - iommus
> + - clocks
> + - clock-names
> + - assigned-clocks
> + - assigned-clock-parents
> + - power-domains
> +
> + additionalProperties: false
> +
> + vcodec-core:
Same here.
> + type: object
> +
> + properties:
> + compatible:
> + const: mediatek,mtk-vcodec-core
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + iommus:
> + minItems: 1
> + maxItems: 32
> + description: |
> + List of the hardware port in respective IOMMU block for current Socs.
> + Refer to bindings/iommu/mediatek,iommu.yaml.
> +
> + clocks:
> + maxItems: 5
> +
> + clock-names:
> + items:
> + - const: sel
> + - const: soc-vdec
> + - const: soc-lat
> + - const: vdec
> + - const: top
> +
> + assigned-clocks:
> + maxItems: 1
> +
> + assigned-clock-parents:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + required:
> + - compatible
> + - reg
> + - interrupts
> + - iommus
> + - clocks
> + - clock-names
> + - assigned-clocks
> + - assigned-clock-parents
> + - power-domains
> +
> + additionalProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - iommus
> + - mediatek,scp
> + - dma-ranges
> + - ranges
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/memory/mt8192-larb-port.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/clock/mt8192-clk.h>
> + #include <dt-bindings/power/mt8192-power.h>
> +
> + video-codec@16000000 {
> + compatible = "mediatek,mt8192-vcodec-dec";
> + mediatek,scp = <&scp>;
> + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x16000000 0x40000>;
> + reg = <0x16000000 0x1000>; /* VDEC_SYS */
> + vcodec-lat@10000 {
> + compatible = "mediatek,mtk-vcodec-lat";
> + reg = <0x10000 0x800>;
> + interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> + <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
> + <&vdecsys_soc CLK_VDEC_SOC_LAT>,
> + <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
> + <&topckgen CLK_TOP_MAINPLL_D4>;
> + clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
> + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
> + };
> +
> + vcodec-core@25000 {
> + compatible = "mediatek,mtk-vcodec-core";
> + reg = <0x25000 0x1000>;
> + interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
> + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> + <&vdecsys CLK_VDEC_VDEC>,
> + <&vdecsys CLK_VDEC_LAT>,
> + <&vdecsys CLK_VDEC_LARB1>,
> + <&topckgen CLK_TOP_MAINPLL_D4>;
> + clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
> + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
> + };
> + };
> --
> 2.25.1
>
>
Hi Rob,
Thanks for your suggestion.
On Fri, 2021-12-10 at 10:49 -0600, Rob Herring wrote:
> On Thu, Dec 02, 2021 at 11:45:40AM +0800, Yunfei Dong wrote:
> > Adds decoder dt-bindings for mt8192.
> >
> > Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
> > ---
> > .../media/mediatek,vcodec-subdev-decoder.yaml | 266
> > ++++++++++++++++++
> > 1 file changed, 266 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-
> > decoder.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-
> > decoder.yaml
> > b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-
> > decoder.yaml
> > new file mode 100644
> > index 000000000000..67cbcf8b3373
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-
> > subdev-decoder.yaml
> > @@ -0,0 +1,266 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +
> > +%YAML 1.2
> > +---
> > +$id: "
> > http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#
> > "
> > +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> > +
> > +title: Mediatek Video Decode Accelerator With Multi Hardware
> > +
> > +maintainers:
> > + - Yunfei Dong <yunfei.dong@mediatek.com>
> > +
> > +description: |
> > + Mediatek Video Decode is the video decode hardware present in
> > Mediatek
> > + SoCs which supports high resolution decoding functionalities.
> > Required
> > + parent and child device node.
> > +
> > + About the Decoder Hardware Block Diagram, please check below:
> > +
> > + +---------------------------------+---------------------------
> > ---------+
> > + | |
> > |
> > + | input -> lat HW -> lat buffer --|--> lat buffer -> core HW
> > -> output |
> > + | || | ||
> > |
> > + +------------||-------------------+---------------------||--
> > -----------+
> > + lat workqueue | core
> > workqueue <parent>
> > + -------------||-----------------------------------------||--
> > ----------------
> > + || ||
> > <child>
> > + \/ <----------------HW index-------------->\/
> > + +----------------------------------------------------
> > --+
> > + | enable/disable
> > |
> > + | clk power irq iommu
> > |
> > + | (lat/lat
> > soc/core0/core1) |
> > + +----------------------------------------------------
> > --+
> > +
> > + As above, there are parent and child devices, child mean each
> > hardware. The child device
> > + controls the information of each hardware independent which
> > include clk/power/irq.
> > +
> > + There are two workqueues in parent device: lat workqueue and
> > core workqueue. They are used
> > + to lat and core hardware deocder. Lat workqueue need to get
> > input bitstream and lat buffer,
> > + then enable lat to decode, writing the result to lat buffer,
> > dislabe hardware when lat decode
> > + done. Core workqueue need to get lat buffer and output buffer,
> > then enable core to decode,
> > + writing the result to output buffer, disable hardware when core
> > decode done. These two
> > + hardwares will decode each frame cyclically.
> > +
> > + For the smi common may not the same for each hardware, can't
> > combine all hardware in one node,
> > + or leading to iommu fault when access dram data.
> > +
> > +properties:
> > + compatible:
> > + const: mediatek,mt8192-vcodec-dec
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + iommus:
> > + minItems: 1
> > + maxItems: 32
> > + description: |
> > + List of the hardware port in respective IOMMU block for
> > current Socs.
> > + Refer to bindings/iommu/mediatek,iommu.yaml.
> > +
> > + mediatek,scp:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + maxItems: 1
> > + description: |
> > + The node of system control processor (SCP), using
> > + the remoteproc & rpmsg framework.
> > + $ref: /schemas/remoteproc/mtk,scp.yaml
>
> '$ref' is not valid here. Just 'See remoteproc/mtk,scp.yaml'
>
Remove this line.
> > +
> > + dma-ranges:
> > + maxItems: 1
> > + description: |
> > + Describes the physical address space of IOMMU maps to
> > memory.
> > +
> > + "#address-cells":
> > + const: 1
> > +
> > + "#size-cells":
> > + const: 1
> > +
> > + ranges: true
> > +
> > +# Required child node:
> > +patternProperties:
> > + vcodec-lat:
>
> '^vcodec-lat@[0-9a-f]+$':
>
Fix in v13.
> > + type: object
> > +
> > + properties:
> > + compatible:
> > + const: mediatek,mtk-vcodec-lat
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + iommus:
> > + minItems: 1
> > + maxItems: 32
> > + description: |
> > + List of the hardware port in respective IOMMU block for
> > current Socs.
> > + Refer to bindings/iommu/mediatek,iommu.yaml.
> > +
> > + clocks:
> > + maxItems: 5
> > +
> > + clock-names:
> > + items:
> > + - const: sel
> > + - const: soc-vdec
> > + - const: soc-lat
> > + - const: vdec
> > + - const: top
> > +
> > + assigned-clocks:
> > + maxItems: 1
> > +
> > + assigned-clock-parents:
> > + maxItems: 1
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - iommus
> > + - clocks
> > + - clock-names
> > + - assigned-clocks
> > + - assigned-clock-parents
> > + - power-domains
> > +
> > + additionalProperties: false
> > +
> > + vcodec-core:
>
> Same here.
Fix in v13.
Thanks,
Yunfei Dong
>
> > + type: object
> > +
> > + properties:
> > + compatible:
> > + const: mediatek,mtk-vcodec-core
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + iommus:
> > + minItems: 1
> > + maxItems: 32
> > + description: |
> > + List of the hardware port in respective IOMMU block for
> > current Socs.
> > + Refer to bindings/iommu/mediatek,iommu.yaml.
> > +
> > + clocks:
> > + maxItems: 5
> > +
> > + clock-names:
> > + items:
> > + - const: sel
> > + - const: soc-vdec
> > + - const: soc-lat
> > + - const: vdec
> > + - const: top
> > +
> > + assigned-clocks:
> > + maxItems: 1
> > +
> > + assigned-clock-parents:
> > + maxItems: 1
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - iommus
> > + - clocks
> > + - clock-names
> > + - assigned-clocks
> > + - assigned-clock-parents
> > + - power-domains
> > +
> > + additionalProperties: false
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - iommus
> > + - mediatek,scp
> > + - dma-ranges
> > + - ranges
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/memory/mt8192-larb-port.h>
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > + #include <dt-bindings/clock/mt8192-clk.h>
> > + #include <dt-bindings/power/mt8192-power.h>
> > +
> > + video-codec@16000000 {
> > + compatible = "mediatek,mt8192-vcodec-dec";
> > + mediatek,scp = <&scp>;
> > + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> > + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0 0x16000000 0x40000>;
> > + reg = <0x16000000 0x1000>; /* VDEC_SYS */
> > + vcodec-lat@10000 {
> > + compatible = "mediatek,mtk-vcodec-lat";
> > + reg = <0x10000 0x800>;
> > + interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
> > + iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> > + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> > + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> > + <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
> > + <&vdecsys_soc CLK_VDEC_SOC_LAT>,
> > + <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
> > + <&topckgen CLK_TOP_MAINPLL_D4>;
> > + clock-names = "sel", "soc-vdec", "soc-lat", "vdec",
> > "top";
> > + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> > + assigned-clock-parents = <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
> > + };
> > +
> > + vcodec-core@25000 {
> > + compatible = "mediatek,mtk-vcodec-core";
> > + reg = <0x25000 0x1000>;
> > + interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
> > + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
> > + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
> > + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
> > + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
> > + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
> > + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
> > + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
> > + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
> > + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
> > + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
> > + <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
> > + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> > + <&vdecsys CLK_VDEC_VDEC>,
> > + <&vdecsys CLK_VDEC_LAT>,
> > + <&vdecsys CLK_VDEC_LARB1>,
> > + <&topckgen CLK_TOP_MAINPLL_D4>;
> > + clock-names = "sel", "soc-vdec", "soc-lat", "vdec",
> > "top";
> > + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> > + assigned-clock-parents = <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
> > + };
> > + };
> > --
> > 2.25.1
> >
> >
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