In CMDQ mode an I/O error in one task (data_crc_err, data_end_bit_err,
etc.) makes the controller raise a halt request. While the halt request
is pending, the controller rejects doorbell writes with a slave response
error, which hangs the CPU (or raises SError on ARM) on Rockchip
platforms.

A software workaround[1] clears CQHCI_CTL right before ringing the
doorbell to narrow down the window, but a race remains: an I/O error can
still happen in another slot between the CQHCI_CTL write and the
doorbell kick, so the hang is not fully solved.

To fix this once and for all, newer silicon introduces
SW_ERR_HALR_REQ_DISABLE (CQHCI_CTL[1]) which stops the controller from
raising a halt request on I/O errors. Set the bit when the CQE is
enabled, which is the last CQHCI_CTL write before any doorbell write.

Older SoCs keep this bit reserved, so writing it is a no-op and nothing
changes in the wild, thus no fixes tag is needed.

[1] https://github.com/rockchip-linux/kernel/commit/4b7ea0500a1a5c186807b737fecfc6bb4d4e06f8
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

---

 drivers/mmc/host/sdhci-of-dwcmshc.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
index 1baa237..0970202 100644
--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
@@ -239,6 +239,8 @@
 					 SDHCI_TRNS_BLK_CNT_EN | \
 					 SDHCI_TRNS_DMA)
 
+#define CQHCI_SW_ERR_HALT_REQ_DISABLE	BIT(1)
+
 #define to_pltfm_data(priv, name) \
 	container_of((priv)->dwcmshc_pdata, struct name##_pltfm_data, dwcmshc_pdata)
 
@@ -702,6 +704,8 @@ static void rk35xx_sdhci_cqe_pre_enable(struct mmc_host *mmc)
 static void rk35xx_sdhci_cqe_enable(struct mmc_host *mmc)
 {
 	struct sdhci_host *host = mmc_priv(mmc);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
 	u32 reg;
 
 	reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
@@ -712,6 +716,15 @@ static void rk35xx_sdhci_cqe_enable(struct mmc_host *mmc)
 
 	sdhci_writew(host, DWCMSHC_SDHCI_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
 
+	/*
+	 * Disable the halt request raised on an I/O error, otherwise a
+	 * doorbell write gets a slave response error while the halt request
+	 * is pending and hangs the CPU. This bit is reserved on older SoCs,
+	 * so the write is a no-op there.
+	 */
+	sdhci_writel(host, CQHCI_SW_ERR_HALT_REQ_DISABLE,
+		     dwc_priv->vendor_specific_area2 + CQHCI_CTL);
+
 	sdhci_cqe_enable(mmc);
 }
 
-- 
2.7.4

On 22/09/2026 12:40, Shawn Lin wrote:
> In CMDQ mode an I/O error in one task (data_crc_err, data_end_bit_err,
> etc.) makes the controller raise a halt request. While the halt request
> is pending, the controller rejects doorbell writes with a slave response
> error, which hangs the CPU (or raises SError on ARM) on Rockchip
> platforms.
> 
> A software workaround[1] clears CQHCI_CTL right before ringing the
> doorbell to narrow down the window, but a race remains: an I/O error can
> still happen in another slot between the CQHCI_CTL write and the
> doorbell kick, so the hang is not fully solved.
> 
> To fix this once and for all, newer silicon introduces
> SW_ERR_HALR_REQ_DISABLE (CQHCI_CTL[1]) which stops the controller from
> raising a halt request on I/O errors. Set the bit when the CQE is
> enabled, which is the last CQHCI_CTL write before any doorbell write.
> 
> Older SoCs keep this bit reserved, so writing it is a no-op and nothing
> changes in the wild, thus no fixes tag is needed.
> 
> [1] https://github.com/rockchip-linux/kernel/commit/4b7ea0500a1a5c186807b737fecfc6bb4d4e06f8
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

Acked-by: Adrian Hunter <adrian.hunter@intel.com>


> 
> ---
> 
>  drivers/mmc/host/sdhci-of-dwcmshc.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
> index 1baa237..0970202 100644
> --- a/drivers/mmc/host/sdhci-of-dwcmshc.c
> +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
> @@ -239,6 +239,8 @@
>  					 SDHCI_TRNS_BLK_CNT_EN | \
>  					 SDHCI_TRNS_DMA)
>  
> +#define CQHCI_SW_ERR_HALT_REQ_DISABLE	BIT(1)
> +
>  #define to_pltfm_data(priv, name) \
>  	container_of((priv)->dwcmshc_pdata, struct name##_pltfm_data, dwcmshc_pdata)
>  
> @@ -702,6 +704,8 @@ static void rk35xx_sdhci_cqe_pre_enable(struct mmc_host *mmc)
>  static void rk35xx_sdhci_cqe_enable(struct mmc_host *mmc)
>  {
>  	struct sdhci_host *host = mmc_priv(mmc);
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
>  	u32 reg;
>  
>  	reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
> @@ -712,6 +716,15 @@ static void rk35xx_sdhci_cqe_enable(struct mmc_host *mmc)
>  
>  	sdhci_writew(host, DWCMSHC_SDHCI_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
>  
> +	/*
> +	 * Disable the halt request raised on an I/O error, otherwise a
> +	 * doorbell write gets a slave response error while the halt request
> +	 * is pending and hangs the CPU. This bit is reserved on older SoCs,
> +	 * so the write is a no-op there.
> +	 */
> +	sdhci_writel(host, CQHCI_SW_ERR_HALT_REQ_DISABLE,
> +		     dwc_priv->vendor_specific_area2 + CQHCI_CTL);
> +
>  	sdhci_cqe_enable(mmc);
>  }
>