drivers/crypto/ccp/psp-dev.c | 8 ++++++-- drivers/crypto/ccp/sp-pci.c | 24 +++++++++++++++++++++++- 2 files changed, 29 insertions(+), 3 deletions(-)
The AMD BC-250 is a Zen 2 APU board (Cyan Skillfish) sold as surplus mining
hardware and now used as a small desktop by a fair number of people. It carries
an AMD Secure Processor at PCI 1022:143e that sp_pci_table[] does not match, so
the device has always been left unbound with its memory windows disabled.
Adding the ID turned out to need two fixes first, both of the same shape: the
driver decides what to bring up from the hardware capability register alone,
and then uses the psp_vdata pointers for those features without checking that
this device has them. On this board the two disagree, because the firmware
advertises a TEE whose ring never comes up.
Patch 1 is a NULL pointer dereference in the sysfs is_visible callback. It
oopses during probe. It needs no new hardware to be reachable in principle:
any device whose firmware sets the TEE capability bit while its psp_vdata
carries no tee data hits it, which today means pspv1 and pspv2 parts. I have
only observed it on the BC-250, so I have not added a stable tag - please add
one if you think it deserves it.
Patch 2 stops a failed optional sub-device from taking down the rest of the
PSP. Without it, a psp_vdata that deliberately omits TEE gets nothing at all,
platform access included.
Patch 3 adds the board. The register layout was read off the device rather
than assumed, and the numbers are in the commit message.
Tested on a BC-250 running 7.2.6. Before:
01:00.2 Encryption controller: AMD Device 143e
Memory at fe700000 [disabled] [size=1M]
Memory at fe884000 [disabled] [size=8K]
(no driver)
After:
ccp 0000:01:00.2: enabling device (0000 -> 0002)
ccp 0000:01:00.2: platform access enabled
ccp 0000:01:00.2: psp enabled
# cat /sys/bus/pci/devices/0000:01:00.2/bootloader_version
00.1c.01.02
with the platform mailbox answering commands. Dynamic boost control is probed
and cleanly rejected by this firmware, and HSTI reports nothing because the
security reporting capability bit is clear. There is no CCP crypto engine
behind this function: the version register at 0x100 reads back all ones.
The series is against v7.2.6 and touches only drivers/crypto/ccp/.
Mattia Tadini (3):
crypto: ccp - fix NULL dereference in psp_firmware_is_visible()
crypto: ccp - do not start PSP sub-devices without their vdata
crypto: ccp - add support for the AMD BC-250 secure processor
drivers/crypto/ccp/psp-dev.c | 8 ++++++--
drivers/crypto/ccp/sp-pci.c | 24 +++++++++++++++++++++++-
2 files changed, 29 insertions(+), 3 deletions(-)
--
2.55.0
On 9/19/26 13:34, Mattia Tadini wrote: > The AMD BC-250 is a Zen 2 APU board (Cyan Skillfish) sold as surplus mining > hardware and now used as a small desktop by a fair number of people. It carries > an AMD Secure Processor at PCI 1022:143e that sp_pci_table[] does not match, so > the device has always been left unbound with its memory windows disabled. > > Adding the ID turned out to need two fixes first, both of the same shape: the > driver decides what to bring up from the hardware capability register alone, > and then uses the psp_vdata pointers for those features without checking that > this device has them. On this board the two disagree, because the firmware > advertises a TEE whose ring never comes up. > > Patch 1 is a NULL pointer dereference in the sysfs is_visible callback. It > oopses during probe. It needs no new hardware to be reachable in principle: > any device whose firmware sets the TEE capability bit while its psp_vdata > carries no tee data hits it, which today means pspv1 and pspv2 parts. I have > only observed it on the BC-250, so I have not added a stable tag - please add > one if you think it deserves it. > > Patch 2 stops a failed optional sub-device from taking down the rest of the > PSP. Without it, a psp_vdata that deliberately omits TEE gets nothing at all, > platform access included. > > Patch 3 adds the board. The register layout was read off the device rather > than assumed, and the numbers are in the commit message. > > Tested on a BC-250 running 7.2.6. Before: > > 01:00.2 Encryption controller: AMD Device 143e > Memory at fe700000 [disabled] [size=1M] > Memory at fe884000 [disabled] [size=8K] > (no driver) > > After: > > ccp 0000:01:00.2: enabling device (0000 -> 0002) > ccp 0000:01:00.2: platform access enabled > ccp 0000:01:00.2: psp enabled > # cat /sys/bus/pci/devices/0000:01:00.2/bootloader_version > 00.1c.01.02 > > with the platform mailbox answering commands. Dynamic boost control is probed > and cleanly rejected by this firmware, and HSTI reports nothing because the > security reporting capability bit is clear. There is no CCP crypto engine > behind this function: the version register at 0x100 reads back all ones. > > The series is against v7.2.6 and touches only drivers/crypto/ccp/. > > Mattia Tadini (3): > crypto: ccp - fix NULL dereference in psp_firmware_is_visible() > crypto: ccp - do not start PSP sub-devices without their vdata > crypto: ccp - add support for the AMD BC-250 secure processor > > drivers/crypto/ccp/psp-dev.c | 8 ++++++-- > drivers/crypto/ccp/sp-pci.c | 24 +++++++++++++++++++++++- > 2 files changed, 29 insertions(+), 3 deletions(-) > Sorry; but what's the point of adding support? You can't access the crypto engine, it doesn't run SEV or TEE, it doesn't support DBC, it doesn't report HSTI. It seems that the capability register isn't even populated on this system. To me it appears the patch series is a lot of "fixes" to let you read.... the bootloader version. Am I missing something else?
On 9/21/26 10:10, Mario Limonciello wrote: > Sorry; but what's the point of adding support? You can't access the > crypto engine, it doesn't run SEV or TEE, it doesn't support DBC, it > doesn't report HSTI. Thanks for looking at it. One correction first, and the mistake is mine: the cover letter is wrong about HSTI. The security reporting bit is clear, but psp_populate_hsti() then asks through the platform access mailbox, and on this board PSP_CMD_HSTI_QUERY does answer. With the series applied on 7.2.6: fused_part=1 debug_lock_on=1 boot_integrity=0 tsme_status=0 anti_rollback_status=0 rom_armor_enforced=0 rpmc_production_enabled=0 rpmc_spirom_available=0 hsp_tpm_available=0 > It seems that the capability register isn't even populated on this > system. It reads 0x00000002, the TEE bit and nothing else. That lone bit, with no TEE behind it, is what patches 1 and 2 are about. > To me it appears the patch series is a lot of "fixes" to let you > read.... the bootloader version. Am I missing something else? Only the above. Once the device is bound, userspace gets the bootloader version (fwupd picks it up as "Secure Processor", bootloader 00.1c.01.02) and the HSTI attributes. Nothing more: no crypto engine, no SEV, no TEE, and the firmware rejects the DBC command. If that is not enough to carry an ID, I understand, and patch 3 can go. Patches 1 and 2 then have no reason to go in either: with the current table I don't know of a shipped part that sets the TEE bit on a pspv1 or pspv2 function, so they would only guard against a device that is not there. So: would you take the series with the HSTI data as the justification for patch 3 (I would send a v2 with a corrected cover letter), or should I drop it? Thanks, Mattia
On 9/22/26 05:05, Mattia Tadini wrote: > On 9/21/26 10:10, Mario Limonciello wrote: >> Sorry; but what's the point of adding support? You can't access the >> crypto engine, it doesn't run SEV or TEE, it doesn't support DBC, it >> doesn't report HSTI. > > Thanks for looking at it. One correction first, and the mistake is > mine: the cover letter is wrong about HSTI. The security reporting bit > is clear, but psp_populate_hsti() then asks through the platform access > mailbox, and on this board PSP_CMD_HSTI_QUERY does answer. With the > series applied on 7.2.6: > > fused_part=1 debug_lock_on=1 > boot_integrity=0 tsme_status=0 > anti_rollback_status=0 rom_armor_enforced=0 > rpmc_production_enabled=0 rpmc_spirom_available=0 > hsp_tpm_available=0 > >> It seems that the capability register isn't even populated on this >> system. > > It reads 0x00000002, the TEE bit and nothing else. That lone bit, with > no TEE behind it, is what patches 1 and 2 are about. > >> To me it appears the patch series is a lot of "fixes" to let you >> read.... the bootloader version. Am I missing something else? > > Only the above. Once the device is bound, userspace gets the bootloader > version (fwupd picks it up as "Secure Processor", bootloader > 00.1c.01.02) and the HSTI attributes. Nothing more: no crypto engine, > no SEV, no TEE, and the firmware rejects the DBC command. > > If that is not enough to carry an ID, I understand, and patch 3 can go. > Patches 1 and 2 then have no reason to go in either: with the current > table I don't know of a shipped part that sets the TEE bit on a pspv1 > or pspv2 function, so they would only guard against a device that is > not there. > > So: would you take the series with the HSTI data as the justification > for patch 3 (I would send a v2 with a corrected cover letter), or > should I drop it? > > Thanks, > Mattia It will be up to Tom here. Given HSTI attributes do get exported from platform access mailbox that does change the shape. But I do think that you should spin it to a v2 for the following reasons: 1) The cover letter is wrong (this discussion). 2) The first patch has a Fixes tag, but it's not really a bug until you add patch 3. So it's in the right place in the series but I don't think it should have a Fixes tag. 3) I'm confused by your comments with TEE. Why is the TEE capabilty set but TEE doesn't work? Is there a problem with a guessed register layout or a real issue? Rather than play whack a mole, wouldn't it be better to just clear psp->capability.tee when the ring init fails? Then you can take pspv3 layout. 4) If you DO end up sticking to a new register layout, you said up front in your cover letter DBC isn't supported. Why do you set PLATFORM_FEATURE_DBC in your platform_features then in patch 3? IMV this isn't going to be a relevant feature in the BC 250. So I think that leaves two options for you to weigh out. A) Either take the existing register pspv3 register layout and clear the TEE capability when the test fails B) Take the new layout you proposed but don't advertise DBC feature.
On 9/22/26 05:33, Mario Limonciello wrote: > > > On 9/22/26 05:05, Mattia Tadini wrote: >> On 9/21/26 10:10, Mario Limonciello wrote: >>> Sorry; but what's the point of adding support? You can't access the >>> crypto engine, it doesn't run SEV or TEE, it doesn't support DBC, it >>> doesn't report HSTI. >> >> Thanks for looking at it. One correction first, and the mistake is >> mine: the cover letter is wrong about HSTI. The security reporting bit >> is clear, but psp_populate_hsti() then asks through the platform access >> mailbox, and on this board PSP_CMD_HSTI_QUERY does answer. With the >> series applied on 7.2.6: >> >> fused_part=1 debug_lock_on=1 >> boot_integrity=0 tsme_status=0 >> anti_rollback_status=0 rom_armor_enforced=0 >> rpmc_production_enabled=0 rpmc_spirom_available=0 >> hsp_tpm_available=0 >> >>> It seems that the capability register isn't even populated on this >>> system. >> >> It reads 0x00000002, the TEE bit and nothing else. That lone bit, with >> no TEE behind it, is what patches 1 and 2 are about. >> >>> To me it appears the patch series is a lot of "fixes" to let you >>> read.... the bootloader version. Am I missing something else? >> >> Only the above. Once the device is bound, userspace gets the bootloader >> version (fwupd picks it up as "Secure Processor", bootloader >> 00.1c.01.02) and the HSTI attributes. Nothing more: no crypto engine, >> no SEV, no TEE, and the firmware rejects the DBC command. >> >> If that is not enough to carry an ID, I understand, and patch 3 can go. >> Patches 1 and 2 then have no reason to go in either: with the current >> table I don't know of a shipped part that sets the TEE bit on a pspv1 >> or pspv2 function, so they would only guard against a device that is >> not there. >> >> So: would you take the series with the HSTI data as the justification >> for patch 3 (I would send a v2 with a corrected cover letter), or >> should I drop it? My take is to just drop it. Thanks, Tom >> >> Thanks, >> Mattia > > It will be up to Tom here. > > Given HSTI attributes do get exported from platform access mailbox that > does change the shape. > > But I do think that you should spin it to a v2 for the following reasons: > > 1) The cover letter is wrong (this discussion). > > 2) The first patch has a Fixes tag, but it's not really a bug until you > add patch 3. So it's in the right place in the series but I don't think > it should have a Fixes tag. > > 3) I'm confused by your comments with TEE. > > Why is the TEE capabilty set but TEE doesn't work? Is there a problem > with a guessed register layout or a real issue? > > Rather than play whack a mole, wouldn't it be better to just clear psp- >>capability.tee when the ring init fails? Then you can take pspv3 layout. > > 4) If you DO end up sticking to a new register layout, you said up front > in your cover letter DBC isn't supported. > > Why do you set PLATFORM_FEATURE_DBC in your platform_features then in > patch 3? IMV this isn't going to be a relevant feature in the BC 250. > > So I think that leaves two options for you to weigh out. > > A) Either take the existing register pspv3 register layout and clear the > TEE capability when the test fails > B) Take the new layout you proposed but don't advertise DBC feature.
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