The following commit has been merged into the perf/core branch of tip:
Commit-ID: 62e074f55f4162e1898e7c1807f1501226a9c393
Gitweb: https://git.kernel.org/tip/62e074f55f4162e1898e7c1807f1501226a9c393
Author: Dapeng Mi <dapeng1.mi@linux.intel.com>
AuthorDate: Mon, 24 Aug 2026 16:27:10 +08:00
Committer: Peter Zijlstra <peterz@infradead.org>
CommitterDate: Wed, 02 Sep 2026 13:10:40 +02:00
perf/x86/intel: Enable large PEBS sampling for XMMs
Modern PEBS hardware supports directly sampling XMM registers, then
large PEBS can be enabled for XMM registers just like other GPRs.
Reported-by: Xudong Hao <xudong.hao@intel.com>
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20260824082731.1013973-3-dapeng1.mi@linux.intel.com
---
arch/x86/events/intel/core.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index cc13164..e412e28 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -4699,7 +4699,8 @@ static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
flags &= ~PERF_SAMPLE_REGS_USER;
if (event->attr.sample_regs_user & ~PEBS_GP_REGS)
flags &= ~PERF_SAMPLE_REGS_USER;
- if (event->attr.sample_regs_intr & ~PEBS_GP_REGS)
+ if (event->attr.sample_regs_intr &
+ ~(PEBS_GP_REGS | PERF_REG_EXTENDED_MASK))
flags &= ~PERF_SAMPLE_REGS_INTR;
return flags;
}