[tip: x86/cpu] x86/cpu/scattered: Sort it properly

tip-bot2 for Borislav Petkov (AMD) posted 1 patch 2 months ago
arch/x86/kernel/cpu/scattered.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
[tip: x86/cpu] x86/cpu/scattered: Sort it properly
Posted by tip-bot2 for Borislav Petkov (AMD) 2 months ago
The following commit has been merged into the x86/cpu branch of tip:

Commit-ID:     cb1e042a320e3c42fae60c4789c2adc618e0833d
Gitweb:        https://git.kernel.org/tip/cb1e042a320e3c42fae60c4789c2adc618e0833d
Author:        Borislav Petkov (AMD) <bp@alien8.de>
AuthorDate:    Fri, 31 Jul 2026 18:52:49 -07:00
Committer:     Borislav Petkov (AMD) <bp@alien8.de>
CommitterDate: Fri, 31 Jul 2026 18:52:49 -07:00

x86/cpu/scattered: Sort it properly

Sort it according to the following precedence of struct cpuid_bit fields:

  (level) -> (sub_leaf) -> (reg) -> (bit).

No functional changes.

Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
---
 arch/x86/kernel/cpu/scattered.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index 937129c..8665a64 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -38,9 +38,9 @@ static const struct cpuid_bit cpuid_bits[] = {
 	{ X86_FEATURE_CQM_MBM_LOCAL,		CPUID_EDX,  2, 0x0000000f, 1 },
 	{ X86_FEATURE_CAT_L3,			CPUID_EBX,  1, 0x00000010, 0 },
 	{ X86_FEATURE_CAT_L2,			CPUID_EBX,  2, 0x00000010, 0 },
+	{ X86_FEATURE_MBA,			CPUID_EBX,  3, 0x00000010, 0 },
 	{ X86_FEATURE_CDP_L3,			CPUID_ECX,  2, 0x00000010, 1 },
 	{ X86_FEATURE_CDP_L2,			CPUID_ECX,  2, 0x00000010, 2 },
-	{ X86_FEATURE_MBA,			CPUID_EBX,  3, 0x00000010, 0 },
 	{ X86_FEATURE_PER_THREAD_MBA,		CPUID_ECX,  0, 0x00000010, 3 },
 	{ X86_FEATURE_SGX1,			CPUID_EAX,  0, 0x00000012, 0 },
 	{ X86_FEATURE_SGX2,			CPUID_EAX,  1, 0x00000012, 0 },
@@ -61,9 +61,9 @@ static const struct cpuid_bit cpuid_bits[] = {
 	{ X86_FEATURE_BMEC,			CPUID_EBX,  3, 0x80000020, 0 },
 	{ X86_FEATURE_ABMC,			CPUID_EBX,  5, 0x80000020, 0 },
 	{ X86_FEATURE_SDCIAE,			CPUID_EBX,  6, 0x80000020, 0 },
+	{ X86_FEATURE_AMD_WORKLOAD_CLASS,	CPUID_EAX, 22, 0x80000021, 0 },
 	{ X86_FEATURE_TSA_SQ_NO,		CPUID_ECX,  1, 0x80000021, 0 },
 	{ X86_FEATURE_TSA_L1_NO,		CPUID_ECX,  2, 0x80000021, 0 },
-	{ X86_FEATURE_AMD_WORKLOAD_CLASS,	CPUID_EAX, 22, 0x80000021, 0 },
 	{ X86_FEATURE_PERFMON_V2,		CPUID_EAX,  0, 0x80000022, 0 },
 	{ X86_FEATURE_AMD_LBR_V2,		CPUID_EAX,  1, 0x80000022, 0 },
 	{ X86_FEATURE_AMD_LBR_PMC_FREEZE,	CPUID_EAX,  2, 0x80000022, 0 },