From: Frank Li <Frank.Li@nxp.com>
Remove cpu_addr_fix() since it is no longer needed. The PCIe ranges
property has been corrected in the DTS, and the DesignWare common code now
handles address translation properly without requiring this workaround.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.x90@mail.toshiba>
---
v3:
Add pci->use_parent_dt_ranges fixes.
Update Signed-off-by address, because my company email address haschanged.
v2:
No Update.
---
drivers/pci/controller/dwc/pcie-visconti.c | 15 ++-------------
1 file changed, 2 insertions(+), 13 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-visconti.c b/drivers/pci/controller/dwc/pcie-visconti.c
index cdeac6177143c..d8765e57147af 100644
--- a/drivers/pci/controller/dwc/pcie-visconti.c
+++ b/drivers/pci/controller/dwc/pcie-visconti.c
@@ -171,20 +171,7 @@ static void visconti_pcie_stop_link(struct dw_pcie *pci)
visconti_mpu_writel(pcie, val | MPU_MP_EN_DISABLE, PCIE_MPU_REG_MP_EN);
}
-/*
- * In this SoC specification, the CPU bus outputs the offset value from
- * 0x40000000 to the PCIe bus, so 0x40000000 is subtracted from the CPU
- * bus address. This 0x40000000 is also based on io_base from DT.
- */
-static u64 visconti_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 cpu_addr)
-{
- struct dw_pcie_rp *pp = &pci->pp;
-
- return cpu_addr & ~pp->io_base;
-}
-
static const struct dw_pcie_ops dw_pcie_ops = {
- .cpu_addr_fixup = visconti_pcie_cpu_addr_fixup,
.link_up = visconti_pcie_link_up,
.start_link = visconti_pcie_start_link,
.stop_link = visconti_pcie_stop_link,
@@ -310,6 +297,8 @@ static int visconti_pcie_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, pcie);
+ pci->use_parent_dt_ranges = true;
+
return visconti_add_pcie_port(pcie, pdev);
}
--
2.51.0In subject, s/PCI: dwc: visconti:/PCI: visconti:/ to match previous
history.
On Mon, Sep 08, 2025 at 11:34:08AM +0900, Nobuhiro Iwamatsu wrote:
> From: Frank Li <Frank.Li@nxp.com>
>
> Remove cpu_addr_fix() since it is no longer needed. The PCIe ranges
> property has been corrected in the DTS, and the DesignWare common code now
> handles address translation properly without requiring this workaround.
As Mani pointed out, the driver has to continue working correctly with
any old DTs in the field.
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.x90@mail.toshiba>
>
> ---
> v3:
> Add pci->use_parent_dt_ranges fixes.
> Update Signed-off-by address, because my company email address haschanged.
>
> v2:
> No Update.
> ---
> drivers/pci/controller/dwc/pcie-visconti.c | 15 ++-------------
> 1 file changed, 2 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-visconti.c b/drivers/pci/controller/dwc/pcie-visconti.c
> index cdeac6177143c..d8765e57147af 100644
> --- a/drivers/pci/controller/dwc/pcie-visconti.c
> +++ b/drivers/pci/controller/dwc/pcie-visconti.c
> @@ -171,20 +171,7 @@ static void visconti_pcie_stop_link(struct dw_pcie *pci)
> visconti_mpu_writel(pcie, val | MPU_MP_EN_DISABLE, PCIE_MPU_REG_MP_EN);
> }
>
> -/*
> - * In this SoC specification, the CPU bus outputs the offset value from
> - * 0x40000000 to the PCIe bus, so 0x40000000 is subtracted from the CPU
> - * bus address. This 0x40000000 is also based on io_base from DT.
> - */
> -static u64 visconti_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 cpu_addr)
> -{
> - struct dw_pcie_rp *pp = &pci->pp;
> -
> - return cpu_addr & ~pp->io_base;
> -}
> -
> static const struct dw_pcie_ops dw_pcie_ops = {
> - .cpu_addr_fixup = visconti_pcie_cpu_addr_fixup,
> .link_up = visconti_pcie_link_up,
> .start_link = visconti_pcie_start_link,
> .stop_link = visconti_pcie_stop_link,
> @@ -310,6 +297,8 @@ static int visconti_pcie_probe(struct platform_device *pdev)
>
> platform_set_drvdata(pdev, pcie);
>
> + pci->use_parent_dt_ranges = true;
> +
> return visconti_add_pcie_port(pcie, pdev);
> }
>
> --
> 2.51.0
>
>
On Mon, Sep 08, 2025 at 04:55:10PM -0500, Bjorn Helgaas wrote:
> In subject, s/PCI: dwc: visconti:/PCI: visconti:/ to match previous
> history.
>
> On Mon, Sep 08, 2025 at 11:34:08AM +0900, Nobuhiro Iwamatsu wrote:
> > From: Frank Li <Frank.Li@nxp.com>
> >
> > Remove cpu_addr_fix() since it is no longer needed. The PCIe ranges
> > property has been corrected in the DTS, and the DesignWare common code now
> > handles address translation properly without requiring this workaround.
>
> As Mani pointed out, the driver has to continue working correctly with
> any old DTs in the field.
DTS should be merged first, then after some linux release cycle, then PCI
can merge this change.
The similar case happen at other area, which broken back compatible. But
we still need move forward.
Frank
>
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.x90@mail.toshiba>
> >
> > ---
> > v3:
> > Add pci->use_parent_dt_ranges fixes.
> > Update Signed-off-by address, because my company email address haschanged.
> >
> > v2:
> > No Update.
> > ---
> > drivers/pci/controller/dwc/pcie-visconti.c | 15 ++-------------
> > 1 file changed, 2 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-visconti.c b/drivers/pci/controller/dwc/pcie-visconti.c
> > index cdeac6177143c..d8765e57147af 100644
> > --- a/drivers/pci/controller/dwc/pcie-visconti.c
> > +++ b/drivers/pci/controller/dwc/pcie-visconti.c
> > @@ -171,20 +171,7 @@ static void visconti_pcie_stop_link(struct dw_pcie *pci)
> > visconti_mpu_writel(pcie, val | MPU_MP_EN_DISABLE, PCIE_MPU_REG_MP_EN);
> > }
> >
> > -/*
> > - * In this SoC specification, the CPU bus outputs the offset value from
> > - * 0x40000000 to the PCIe bus, so 0x40000000 is subtracted from the CPU
> > - * bus address. This 0x40000000 is also based on io_base from DT.
> > - */
> > -static u64 visconti_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 cpu_addr)
> > -{
> > - struct dw_pcie_rp *pp = &pci->pp;
> > -
> > - return cpu_addr & ~pp->io_base;
> > -}
> > -
> > static const struct dw_pcie_ops dw_pcie_ops = {
> > - .cpu_addr_fixup = visconti_pcie_cpu_addr_fixup,
> > .link_up = visconti_pcie_link_up,
> > .start_link = visconti_pcie_start_link,
> > .stop_link = visconti_pcie_stop_link,
> > @@ -310,6 +297,8 @@ static int visconti_pcie_probe(struct platform_device *pdev)
> >
> > platform_set_drvdata(pdev, pcie);
> >
> > + pci->use_parent_dt_ranges = true;
> > +
> > return visconti_add_pcie_port(pcie, pdev);
> > }
> >
> > --
> > 2.51.0
> >
> >
On Wed, Sep 10, 2025 at 12:10:10PM GMT, Frank Li wrote: > On Mon, Sep 08, 2025 at 04:55:10PM -0500, Bjorn Helgaas wrote: > > In subject, s/PCI: dwc: visconti:/PCI: visconti:/ to match previous > > history. > > > > On Mon, Sep 08, 2025 at 11:34:08AM +0900, Nobuhiro Iwamatsu wrote: > > > From: Frank Li <Frank.Li@nxp.com> > > > > > > Remove cpu_addr_fix() since it is no longer needed. The PCIe ranges > > > property has been corrected in the DTS, and the DesignWare common code now > > > handles address translation properly without requiring this workaround. > > > > As Mani pointed out, the driver has to continue working correctly with > > any old DTs in the field. > > DTS should be merged first, then after some linux release cycle, then PCI > can merge this change. > > The similar case happen at other area, which broken back compatible. But > we still need move forward. > Absolutely not! DT is a firmware. Even though the firmware turns out to be buggy, we should not regress platforms that were using the old firmware. We can surely remove the check after some time. Maybe when all the stable kernels stop supporting older DTs. But not until then. - Mani -- மணிவண்ணன் சதாசிவம்
On Mon, Sep 08, 2025 at 11:34:08AM GMT, Nobuhiro Iwamatsu wrote:
> From: Frank Li <Frank.Li@nxp.com>
>
> Remove cpu_addr_fix() since it is no longer needed. The PCIe ranges
> property has been corrected in the DTS, and the DesignWare common code now
> handles address translation properly without requiring this workaround.
>
What about the old DTs? Wouldn't this driver fail to work if you use it with old
DTs as cpu_addr_fixup() no longer exists?
- Mani
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.x90@mail.toshiba>
>
> ---
> v3:
> Add pci->use_parent_dt_ranges fixes.
> Update Signed-off-by address, because my company email address haschanged.
>
> v2:
> No Update.
> ---
> drivers/pci/controller/dwc/pcie-visconti.c | 15 ++-------------
> 1 file changed, 2 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-visconti.c b/drivers/pci/controller/dwc/pcie-visconti.c
> index cdeac6177143c..d8765e57147af 100644
> --- a/drivers/pci/controller/dwc/pcie-visconti.c
> +++ b/drivers/pci/controller/dwc/pcie-visconti.c
> @@ -171,20 +171,7 @@ static void visconti_pcie_stop_link(struct dw_pcie *pci)
> visconti_mpu_writel(pcie, val | MPU_MP_EN_DISABLE, PCIE_MPU_REG_MP_EN);
> }
>
> -/*
> - * In this SoC specification, the CPU bus outputs the offset value from
> - * 0x40000000 to the PCIe bus, so 0x40000000 is subtracted from the CPU
> - * bus address. This 0x40000000 is also based on io_base from DT.
> - */
> -static u64 visconti_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 cpu_addr)
> -{
> - struct dw_pcie_rp *pp = &pci->pp;
> -
> - return cpu_addr & ~pp->io_base;
> -}
> -
> static const struct dw_pcie_ops dw_pcie_ops = {
> - .cpu_addr_fixup = visconti_pcie_cpu_addr_fixup,
> .link_up = visconti_pcie_link_up,
> .start_link = visconti_pcie_start_link,
> .stop_link = visconti_pcie_stop_link,
> @@ -310,6 +297,8 @@ static int visconti_pcie_probe(struct platform_device *pdev)
>
> platform_set_drvdata(pdev, pcie);
>
> + pci->use_parent_dt_ranges = true;
> +
> return visconti_add_pcie_port(pcie, pdev);
> }
>
> --
> 2.51.0
>
>
--
மணிவண்ணன் சதாசிவம்
© 2016 - 2025 Red Hat, Inc.