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[PATCH v3 1/2] arm64: dts: toshiba: Update SoC and PCIe ranges to reflect hardware behavior

Nobuhiro Iwamatsu posted 2 patches 3 months, 1 week ago
[PATCH v3 1/2] arm64: dts: toshiba: Update SoC and PCIe ranges to reflect hardware behavior
Posted by Nobuhiro Iwamatsu 3 months, 1 week ago 
From: Frank Li <Frank.Li@nxp.com>

tmpv7708 trim address bit[31:30] in tmpv7708 before passing to the PCIe
controller. Since only PCIe controller needs to convert the address range
0x40000000 - 0x80000000, add a bus definition, describe the ranges in it,
and move the PCIe definition.

Prepare for the removal of the driver’s cpu_addr_fixup().

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Suggested-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.x90@mail.toshiba>

---
v3:
 Move update in drivers/pci/controller/dwc/pcie-visconti.c to patch 2.
 Update Signed-off-by address, because my company email address has changed.

v2:
  Update commit message.
  Fix range.
  Set true to use_parent_dt_ranges.
  move pcie under the dedicated sub-bus.
---
 arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 75 ++++++++++++++---------
 1 file changed, 45 insertions(+), 30 deletions(-)

diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
index 39806f0ae5133..b754965a76ca6 100644
--- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
+++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
@@ -478,37 +478,52 @@ pwm: pwm@241c0000 {
 			status = "disabled";
 		};
 
-		pcie: pcie@28400000 {
-			compatible = "toshiba,visconti-pcie";
-			reg = <0x0 0x28400000 0x0 0x00400000>,
-			      <0x0 0x70000000 0x0 0x10000000>,
-			      <0x0 0x28050000 0x0 0x00010000>,
-			      <0x0 0x24200000 0x0 0x00002000>,
-			      <0x0 0x24162000 0x0 0x00001000>;
-			reg-names = "dbi", "config", "ulreg", "smu", "mpu";
-			device_type = "pci";
-			bus-range = <0x00 0xff>;
-			num-lanes = <2>;
-			num-viewport = <8>;
-
-			#address-cells = <3>;
+		pcie_bus: bus@24000000 {
+			compatible = "simple-bus";
+			#address-cells = <2>;
 			#size-cells = <2>;
-			#interrupt-cells = <1>;
-			ranges = <0x81000000 0 0x40000000 0 0x40000000 0 0x00010000
-				  0x82000000 0 0x50000000 0 0x50000000 0 0x20000000>;
-			interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "msi", "intr";
-			interrupt-map-mask = <0 0 0 7>;
-			interrupt-map =
-				<0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
-				 0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
-				 0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
-				 0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
-			max-link-speed = <2>;
-			clocks = <&extclk100mhz>, <&pismu TMPV770X_CLK_PCIE_MSTR>, <&pismu TMPV770X_CLK_PCIE_AUX>;
-			clock-names = "ref", "core", "aux";
-			status = "disabled";
+			ranges = /* register 1:1 map */
+				 <0x0 0x24000000 0x0 0x24000000 0x0 0x0C000000>,
+				 /*
+				  * bus fabric mask address bit 30 and 31 to 0
+				  * before send to PCIe controller.
+				  *
+				  * PCIe map address 0 to cpu's 0x40000000
+				  */
+				 <0x0 0x00000000 0x0 0x40000000 0x0 0x40000000>;
+
+			pcie: pcie@28400000 {
+				compatible = "toshiba,visconti-pcie";
+				reg = <0x0 0x28400000 0x0 0x00400000>,
+				      <0x0 0x30000000 0x0 0x10000000>,
+				      <0x0 0x28050000 0x0 0x00010000>,
+				      <0x0 0x24200000 0x0 0x00002000>,
+				      <0x0 0x24162000 0x0 0x00001000>;
+				reg-names = "dbi", "config", "ulreg", "smu", "mpu";
+				device_type = "pci";
+				bus-range = <0x00 0xff>;
+				num-lanes = <2>;
+				num-viewport = <8>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				#interrupt-cells = <1>;
+				ranges = <0x81000000 0 0x00000000 0 0x00000000 0 0x00010000
+					  0x82000000 0 0x10000000 0 0x10000000 0 0x20000000>;
+				interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "msi", "intr";
+				interrupt-map-mask = <0 0 0 7>;
+				interrupt-map =
+					<0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
+					 0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
+					 0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
+					 0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+				max-link-speed = <2>;
+				clocks = <&extclk100mhz>, <&pismu TMPV770X_CLK_PCIE_MSTR>, <&pismu TMPV770X_CLK_PCIE_AUX>;
+				clock-names = "ref", "core", "aux";
+				status = "disabled";
+			};
 		};
 	};
 };
-- 
2.51.0
Re: [PATCH v3 1/2] arm64: dts: toshiba: Update SoC and PCIe ranges to reflect hardware behavior
Posted by Manivannan Sadhasivam 1 month, 4 weeks ago 
On Mon, Sep 08, 2025 at 11:34:07AM +0900, Nobuhiro Iwamatsu wrote:
> From: Frank Li <Frank.Li@nxp.com>
> 
> tmpv7708 trim address bit[31:30] in tmpv7708 before passing to the PCIe
> controller. Since only PCIe controller needs to convert the address range
> 0x40000000 - 0x80000000, add a bus definition, describe the ranges in it,
> and move the PCIe definition.
> 
> Prepare for the removal of the driver’s cpu_addr_fixup().
> 

This statement is the linux driver behavior which has nothing to do with
devicetree. Please drop it.

> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> Suggested-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.x90@mail.toshiba>

Acked-by: Manivannan Sadhasivam <mani@kernel.org>

- Mani

> 
> ---
> v3:
>  Move update in drivers/pci/controller/dwc/pcie-visconti.c to patch 2.
>  Update Signed-off-by address, because my company email address has changed.
> 
> v2:
>   Update commit message.
>   Fix range.
>   Set true to use_parent_dt_ranges.
>   move pcie under the dedicated sub-bus.
> ---
>  arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 75 ++++++++++++++---------
>  1 file changed, 45 insertions(+), 30 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
> index 39806f0ae5133..b754965a76ca6 100644
> --- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
> +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
> @@ -478,37 +478,52 @@ pwm: pwm@241c0000 {
>  			status = "disabled";
>  		};
>  
> -		pcie: pcie@28400000 {
> -			compatible = "toshiba,visconti-pcie";
> -			reg = <0x0 0x28400000 0x0 0x00400000>,
> -			      <0x0 0x70000000 0x0 0x10000000>,
> -			      <0x0 0x28050000 0x0 0x00010000>,
> -			      <0x0 0x24200000 0x0 0x00002000>,
> -			      <0x0 0x24162000 0x0 0x00001000>;
> -			reg-names = "dbi", "config", "ulreg", "smu", "mpu";
> -			device_type = "pci";
> -			bus-range = <0x00 0xff>;
> -			num-lanes = <2>;
> -			num-viewport = <8>;
> -
> -			#address-cells = <3>;
> +		pcie_bus: bus@24000000 {
> +			compatible = "simple-bus";
> +			#address-cells = <2>;
>  			#size-cells = <2>;
> -			#interrupt-cells = <1>;
> -			ranges = <0x81000000 0 0x40000000 0 0x40000000 0 0x00010000
> -				  0x82000000 0 0x50000000 0 0x50000000 0 0x20000000>;
> -			interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
> -				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
> -			interrupt-names = "msi", "intr";
> -			interrupt-map-mask = <0 0 0 7>;
> -			interrupt-map =
> -				<0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
> -				 0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
> -				 0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
> -				 0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
> -			max-link-speed = <2>;
> -			clocks = <&extclk100mhz>, <&pismu TMPV770X_CLK_PCIE_MSTR>, <&pismu TMPV770X_CLK_PCIE_AUX>;
> -			clock-names = "ref", "core", "aux";
> -			status = "disabled";
> +			ranges = /* register 1:1 map */
> +				 <0x0 0x24000000 0x0 0x24000000 0x0 0x0C000000>,
> +				 /*
> +				  * bus fabric mask address bit 30 and 31 to 0
> +				  * before send to PCIe controller.
> +				  *
> +				  * PCIe map address 0 to cpu's 0x40000000
> +				  */
> +				 <0x0 0x00000000 0x0 0x40000000 0x0 0x40000000>;
> +
> +			pcie: pcie@28400000 {
> +				compatible = "toshiba,visconti-pcie";
> +				reg = <0x0 0x28400000 0x0 0x00400000>,
> +				      <0x0 0x30000000 0x0 0x10000000>,
> +				      <0x0 0x28050000 0x0 0x00010000>,
> +				      <0x0 0x24200000 0x0 0x00002000>,
> +				      <0x0 0x24162000 0x0 0x00001000>;
> +				reg-names = "dbi", "config", "ulreg", "smu", "mpu";
> +				device_type = "pci";
> +				bus-range = <0x00 0xff>;
> +				num-lanes = <2>;
> +				num-viewport = <8>;
> +
> +				#address-cells = <3>;
> +				#size-cells = <2>;
> +				#interrupt-cells = <1>;
> +				ranges = <0x81000000 0 0x00000000 0 0x00000000 0 0x00010000
> +					  0x82000000 0 0x10000000 0 0x10000000 0 0x20000000>;
> +				interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-names = "msi", "intr";
> +				interrupt-map-mask = <0 0 0 7>;
> +				interrupt-map =
> +					<0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
> +					 0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
> +					 0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
> +					 0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
> +				max-link-speed = <2>;
> +				clocks = <&extclk100mhz>, <&pismu TMPV770X_CLK_PCIE_MSTR>, <&pismu TMPV770X_CLK_PCIE_AUX>;
> +				clock-names = "ref", "core", "aux";
> +				status = "disabled";
> +			};
>  		};
>  	};
>  };
> -- 
> 2.51.0
> 
> 

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