[tip: x86/msr] x86/msr: Rename 'wrmsrl_cstar()' to 'wrmsrq_cstar()'

tip-bot2 for Ingo Molnar posted 1 patch 8 months, 1 week ago
arch/x86/kernel/cpu/common.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
[tip: x86/msr] x86/msr: Rename 'wrmsrl_cstar()' to 'wrmsrq_cstar()'
Posted by tip-bot2 for Ingo Molnar 8 months, 1 week ago
The following commit has been merged into the x86/msr branch of tip:

Commit-ID:     eef476f15c8350078efb48bd9b9f3ff50ae1bbbb
Gitweb:        https://git.kernel.org/tip/eef476f15c8350078efb48bd9b9f3ff50ae1bbbb
Author:        Ingo Molnar <mingo@kernel.org>
AuthorDate:    Wed, 09 Apr 2025 22:29:07 +02:00
Committer:     Ingo Molnar <mingo@kernel.org>
CommitterDate: Thu, 10 Apr 2025 11:59:37 +02:00

x86/msr: Rename 'wrmsrl_cstar()' to 'wrmsrq_cstar()'

Suggested-by: "H. Peter Anvin" <hpa@zytor.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Juergen Gross <jgross@suse.com>
Cc: Dave Hansen <dave.hansen@intel.com>
Cc: Xin Li <xin@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
---
 arch/x86/kernel/cpu/common.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index bb986ba..079ded4 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -2091,7 +2091,7 @@ DEFINE_PER_CPU_CACHE_HOT(unsigned long, cpu_current_top_of_stack) = TOP_OF_INIT_
 DEFINE_PER_CPU_CACHE_HOT(u64, __x86_call_depth);
 EXPORT_PER_CPU_SYMBOL(__x86_call_depth);
 
-static void wrmsrl_cstar(unsigned long val)
+static void wrmsrq_cstar(unsigned long val)
 {
 	/*
 	 * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR
@@ -2107,7 +2107,7 @@ static inline void idt_syscall_init(void)
 	wrmsrq(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
 
 	if (ia32_enabled()) {
-		wrmsrl_cstar((unsigned long)entry_SYSCALL_compat);
+		wrmsrq_cstar((unsigned long)entry_SYSCALL_compat);
 		/*
 		 * This only works on Intel CPUs.
 		 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
@@ -2119,7 +2119,7 @@ static inline void idt_syscall_init(void)
 			    (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1));
 		wrmsrq_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
 	} else {
-		wrmsrl_cstar((unsigned long)entry_SYSCALL32_ignore);
+		wrmsrq_cstar((unsigned long)entry_SYSCALL32_ignore);
 		wrmsrq_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
 		wrmsrq_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
 		wrmsrq_safe(MSR_IA32_SYSENTER_EIP, 0ULL);