From: Tristram Ha <tristram.ha@microchip.com>

The initial code used 32-bit register.  After that it was changed to 0x1F
so it is no longer appropriate to use 32-bit write.

Fixes: e1add7dd6183 ("net: dsa: microchip: use common irq routines for girq and pirq")
Signed-off-by: Tristram Ha <tristram.ha@microchip.com>
---
 drivers/net/dsa/microchip/ksz_common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
index 1e0085cd9a9a..3ad0879b00cd 100644
--- a/drivers/net/dsa/microchip/ksz_common.c
+++ b/drivers/net/dsa/microchip/ksz_common.c
@@ -2185,7 +2185,7 @@ static void ksz_irq_bus_sync_unlock(struct irq_data *d)
 	struct ksz_device *dev = kirq->dev;
 	int ret;
 
-	ret = ksz_write32(dev, kirq->reg_mask, kirq->masked);
+	ret = ksz_write8(dev, kirq->reg_mask, kirq->masked);
 	if (ret)
 		dev_err(dev->dev, "failed to change IRQ mask\n");
 
-- 
2.34.1

On Tue, 2024-05-28 at 14:35 -0700, Tristram.Ha@microchip.com wrote:
> From: Tristram Ha <tristram.ha@microchip.com>
> 
> The initial code used 32-bit register.  After that it was changed to 0x1F
> so it is no longer appropriate to use 32-bit write.

IMHO the above sentence is too much unclear. It sort of implies that
the currently used register is 8 bit wide because such register address
can be represented with 8 bit - which in turn sounds weird or
irrelevant.

I guess some documentation describes register 0x1F, please rephrase the
changelog accordingly.

Thanks,

Paolo

> Subject: Re: [PATCH net] net: dsa: microchip: fix wrong register write when masking
> interrupt
> 
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> On Tue, 2024-05-28 at 14:35 -0700, Tristram.Ha@microchip.com wrote:
> > From: Tristram Ha <tristram.ha@microchip.com>
> >
> > The initial code used 32-bit register.  After that it was changed to 0x1F
> > so it is no longer appropriate to use 32-bit write.
> 
> IMHO the above sentence is too much unclear. It sort of implies that
> the currently used register is 8 bit wide because such register address
> can be represented with 8 bit - which in turn sounds weird or
> irrelevant.
> 
> I guess some documentation describes register 0x1F, please rephrase the
> changelog accordingly.

I will clarify the comment.
Initially the REG_SW_PORT_INT_MASK__4 is defined as 0x001C in
ksz9477_reg.h and REG_PORT_INT_MASK is defined as 0x#01F.  Because the
global and port interrupt handling is about the same new
REG_SW_PORT_INT_MASK__1 is defined as 0x1F in ksz_common.h.  This works
as only the least significant bits have effect.  As a result the 32-bit
write needs to be changed to 8-bit.