Adding iommus property and setting max link speed for PCIe

[PATCH v1 2/2] arm64: dts: qcom: sa8775p: Set max link speed to gen4 for ep pcie

Posted by Mrinmay Sarkar 1 year, 7 months ago

Adding this change to set max link speed to gen4 as sa8775p supports
gen4 so that pcie link can be enumerated as gen4.

Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 0c52180..aad2cd7 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -3730,7 +3730,7 @@
 		power-domains = <&gcc PCIE_0_GDSC>;
 		phys = <&pcie0_phy>;
 		phy-names = "pciephy";
-		max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
+		max-link-speed = <4>;
 		num-lanes = <2>;
 
 		status = "disabled";
@@ -3888,7 +3888,7 @@
 		power-domains = <&gcc PCIE_1_GDSC>;
 		phys = <&pcie1_phy>;
 		phy-names = "pciephy";
-		max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
+		max-link-speed = <4>;
 		num-lanes = <4>;
 
 		status = "disabled";
-- 
2.7.4

Re: [PATCH v1 2/2] arm64: dts: qcom: sa8775p: Set max link speed to gen4 for ep pcie

Posted by Dmitry Baryshkov 1 year, 7 months ago

On Tue, 30 Apr 2024 at 19:33, Mrinmay Sarkar <quic_msarkar@quicinc.com> wrote:
>
> Adding this change to set max link speed to gen4 as sa8775p supports
> gen4 so that pcie link can be enumerated as gen4.

Previous patches mentioned stability issues. Were they solved?


>
> Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sa8775p.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index 0c52180..aad2cd7 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -3730,7 +3730,7 @@
>                 power-domains = <&gcc PCIE_0_GDSC>;
>                 phys = <&pcie0_phy>;
>                 phy-names = "pciephy";
> -               max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
> +               max-link-speed = <4>;
>                 num-lanes = <2>;
>
>                 status = "disabled";
> @@ -3888,7 +3888,7 @@
>                 power-domains = <&gcc PCIE_1_GDSC>;
>                 phys = <&pcie1_phy>;
>                 phy-names = "pciephy";
> -               max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */

I think you've just sent a patchset which adds this node. Is there any
reason for setting the max-link-speed to 3 just to change it to 4
immediately?

> +               max-link-speed = <4>;
>                 num-lanes = <4>;
>
>                 status = "disabled";
> --
> 2.7.4
>
>


--
With best wishes

Dmitry

Re: [PATCH v1 2/2] arm64: dts: qcom: sa8775p: Set max link speed to gen4 for ep pcie

Posted by Mrinmay Sarkar 1 year, 7 months ago

On 4/30/2024 11:20 PM, Dmitry Baryshkov wrote:
> On Tue, 30 Apr 2024 at 19:33, Mrinmay Sarkar <quic_msarkar@quicinc.com> wrote:
>> Adding this change to set max link speed to gen4 as sa8775p supports
>> gen4 so that pcie link can be enumerated as gen4.
> Previous patches mentioned stability issues. Were they solved?
Hi Dmitry,
Thanks for review.

Actually earlier gen4 related equalization setting was missing in driver.
That's why gen4 was not stable and it was coming to gen3.

With this below driver change gen4 is stable now
https://lore.kernel.org/all/20240501163610.8900-1-quic_schintav@quicinc.com/ 

>> Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/sa8775p.dtsi | 4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> index 0c52180..aad2cd7 100644
>> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> @@ -3730,7 +3730,7 @@
>>                  power-domains = <&gcc PCIE_0_GDSC>;
>>                  phys = <&pcie0_phy>;
>>                  phy-names = "pciephy";
>> -               max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
>> +               max-link-speed = <4>;
>>                  num-lanes = <2>;
>>
>>                  status = "disabled";
>> @@ -3888,7 +3888,7 @@
>>                  power-domains = <&gcc PCIE_1_GDSC>;
>>                  phys = <&pcie1_phy>;
>>                  phy-names = "pciephy";
>> -               max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
> I think you've just sent a patchset which adds this node. Is there any
> reason for setting the max-link-speed to 3 just to change it to 4
> immediately?
Earlier we were not sure about the root cause of the issue
so limited the speed to gen3. Now as we have the solution
for this issue so moving to gen4.
> Thanks,
> Mrinmay
>> +               max-link-speed = <4>;
>>                  num-lanes = <4>;
>>
>>                  status = "disabled";
>> --
>> 2.7.4
>>
>>
>
> --
> With best wishes
>
> Dmitry