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[PATCH v2] usb: dwc3: core: enable CCI support for AMD-xilinx DWC3 controller

Radhey Shyam Pandey posted 1 patch 1 year, 11 months ago 
drivers/usb/dwc3/core.c | 26 ++++++++++++++++++++++++++
drivers/usb/dwc3/core.h |  5 +++++
2 files changed, 31 insertions(+)
[PATCH v2] usb: dwc3: core: enable CCI support for AMD-xilinx DWC3 controller
Posted by Radhey Shyam Pandey 1 year, 11 months ago 
From: Piyush Mehta <piyush.mehta@amd.com>

The GSBUSCFG0 register bits [31:16] are used to configure the cache type
settings of the descriptor and data write/read transfers (Cacheable,
Bufferable/ Posted). When CCI is enabled in the design, DWC3 core GSBUSCFG0
cache bits must be updated to support CCI enabled transfers in USB.

Signed-off-by: Piyush Mehta <piyush.mehta@amd.com>
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
----
changes for v2:
Make GSBUSCFG0 configuration specific to AMD-xilinx platform.
Taken reference from existing commit ec5eb43813a4 ("usb: dwc3: core:
add support for realtek SoCs custom's global register start address")

v1 link:
https://lore.kernel.org/all/20231013053448.11056-1-piyush.mehta@amd.com
---
 drivers/usb/dwc3/core.c | 26 ++++++++++++++++++++++++++
 drivers/usb/dwc3/core.h |  5 +++++
 2 files changed, 31 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 3e55838c0001..3acd4ab3fcca 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -23,6 +23,7 @@
 #include <linux/delay.h>
 #include <linux/dma-mapping.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/of_graph.h>
 #include <linux/acpi.h>
 #include <linux/pinctrl/consumer.h>
@@ -559,6 +560,29 @@ static void dwc3_cache_hwparams(struct dwc3 *dwc)
 		parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
 }
 
+static void dwc3_config_soc_bus(struct dwc3 *dwc)
+{
+	if (dwc->dev->of_node) {
+		struct device_node *parent = of_get_parent(dwc->dev->of_node);
+
+		if (of_device_is_compatible(parent, "xlnx,zynqmp-dwc3") ||
+		    of_device_is_compatible(parent, "xlnx,versal-dwc3")) {
+			if (of_dma_is_coherent(dwc->dev->of_node)) {
+				u32 reg;
+
+				reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
+				reg |= DWC3_GSBUSCFG0_DATRDREQINFO_MASK |
+					DWC3_GSBUSCFG0_DESRDREQINFO_MASK |
+					DWC3_GSBUSCFG0_DATWRREQINFO_MASK |
+					DWC3_GSBUSCFG0_DESWRREQINFO_MASK;
+				dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
+			}
+		}
+
+		of_node_put(parent);
+	}
+}
+
 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
 {
 	int intf;
@@ -1256,6 +1280,8 @@ static int dwc3_core_init(struct dwc3 *dwc)
 
 	dwc3_set_incr_burst_type(dwc);
 
+	dwc3_config_soc_bus(dwc);
+
 	ret = dwc3_phy_power_on(dwc);
 	if (ret)
 		goto err_exit_phy;
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 25dc0599345e..bf19a20e240f 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -175,6 +175,11 @@
 #define DWC3_LLUCTL		0xd024
 
 /* Bit fields */
+/* Global SoC Bus Configuration Register: AHB-prot/AXI-cache/OCP-ReqInfo */
+#define DWC3_GSBUSCFG0_DATRDREQINFO_MASK	GENMASK(31, 28)
+#define DWC3_GSBUSCFG0_DESRDREQINFO_MASK	GENMASK(27, 24)
+#define DWC3_GSBUSCFG0_DATWRREQINFO_MASK	GENMASK(23, 20)
+#define DWC3_GSBUSCFG0_DESWRREQINFO_MASK	GENMASK(19, 16)
 
 /* Global SoC Bus Configuration INCRx Register 0 */
 #define DWC3_GSBUSCFG0_INCR256BRSTENA	(1 << 7) /* INCR256 burst */
-- 
2.34.1
Re: [PATCH v2] usb: dwc3: core: enable CCI support for AMD-xilinx DWC3 controller
Posted by Thinh Nguyen 1 year, 11 months ago 
On Sat, Feb 24, 2024, Radhey Shyam Pandey wrote:
> From: Piyush Mehta <piyush.mehta@amd.com>
> 
> The GSBUSCFG0 register bits [31:16] are used to configure the cache type
> settings of the descriptor and data write/read transfers (Cacheable,
> Bufferable/ Posted). When CCI is enabled in the design, DWC3 core GSBUSCFG0
> cache bits must be updated to support CCI enabled transfers in USB.
> 
> Signed-off-by: Piyush Mehta <piyush.mehta@amd.com>
> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
> ----
> changes for v2:
> Make GSBUSCFG0 configuration specific to AMD-xilinx platform.
> Taken reference from existing commit ec5eb43813a4 ("usb: dwc3: core:
> add support for realtek SoCs custom's global register start address")
> 
> v1 link:
> https://urldefense.com/v3/__https://lore.kernel.org/all/20231013053448.11056-1-piyush.mehta@amd.com__;!!A4F2R9G_pg!ffADlNJmRyCb1C2B0z21-8AbJE4YDyiXNxKBKBqmhmBOSSZBokHS_qyetGEqb7Cwawe0Wvbz2aqSZz_bTfvS0cXdwXLVWw$ 

Please check the comment from the previous thread:
https://lore.kernel.org/linux-usb/20240223224744.vptvfkqzgqv24ptz@synopsys.com/T/#t

Thanks,
Thinh

> ---
>  drivers/usb/dwc3/core.c | 26 ++++++++++++++++++++++++++
>  drivers/usb/dwc3/core.h |  5 +++++
>  2 files changed, 31 insertions(+)
> 
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 3e55838c0001..3acd4ab3fcca 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -23,6 +23,7 @@
>  #include <linux/delay.h>
>  #include <linux/dma-mapping.h>
>  #include <linux/of.h>
> +#include <linux/of_address.h>
>  #include <linux/of_graph.h>
>  #include <linux/acpi.h>
>  #include <linux/pinctrl/consumer.h>
> @@ -559,6 +560,29 @@ static void dwc3_cache_hwparams(struct dwc3 *dwc)
>  		parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
>  }
>  
> +static void dwc3_config_soc_bus(struct dwc3 *dwc)
> +{
> +	if (dwc->dev->of_node) {
> +		struct device_node *parent = of_get_parent(dwc->dev->of_node);
> +
> +		if (of_device_is_compatible(parent, "xlnx,zynqmp-dwc3") ||
> +		    of_device_is_compatible(parent, "xlnx,versal-dwc3")) {
> +			if (of_dma_is_coherent(dwc->dev->of_node)) {
> +				u32 reg;
> +
> +				reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
> +				reg |= DWC3_GSBUSCFG0_DATRDREQINFO_MASK |
> +					DWC3_GSBUSCFG0_DESRDREQINFO_MASK |
> +					DWC3_GSBUSCFG0_DATWRREQINFO_MASK |
> +					DWC3_GSBUSCFG0_DESWRREQINFO_MASK;
> +				dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
> +			}
> +		}
> +
> +		of_node_put(parent);
> +	}
> +}
> +
>  static int dwc3_core_ulpi_init(struct dwc3 *dwc)
>  {
>  	int intf;
> @@ -1256,6 +1280,8 @@ static int dwc3_core_init(struct dwc3 *dwc)
>  
>  	dwc3_set_incr_burst_type(dwc);
>  
> +	dwc3_config_soc_bus(dwc);
> +
>  	ret = dwc3_phy_power_on(dwc);
>  	if (ret)
>  		goto err_exit_phy;
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index 25dc0599345e..bf19a20e240f 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -175,6 +175,11 @@
>  #define DWC3_LLUCTL		0xd024
>  
>  /* Bit fields */
> +/* Global SoC Bus Configuration Register: AHB-prot/AXI-cache/OCP-ReqInfo */
> +#define DWC3_GSBUSCFG0_DATRDREQINFO_MASK	GENMASK(31, 28)
> +#define DWC3_GSBUSCFG0_DESRDREQINFO_MASK	GENMASK(27, 24)
> +#define DWC3_GSBUSCFG0_DATWRREQINFO_MASK	GENMASK(23, 20)
> +#define DWC3_GSBUSCFG0_DESWRREQINFO_MASK	GENMASK(19, 16)
>  
>  /* Global SoC Bus Configuration INCRx Register 0 */
>  #define DWC3_GSBUSCFG0_INCR256BRSTENA	(1 << 7) /* INCR256 burst */
> -- 
> 2.34.1
>
Re: [PATCH v2] usb: dwc3: core: enable CCI support for AMD-xilinx DWC3 controller
Posted by Thinh Nguyen 1 year, 11 months ago 
On Fri, Feb 23, 2024, Thinh Nguyen wrote:
> On Sat, Feb 24, 2024, Radhey Shyam Pandey wrote:
> > From: Piyush Mehta <piyush.mehta@amd.com>
> > 
> > The GSBUSCFG0 register bits [31:16] are used to configure the cache type
> > settings of the descriptor and data write/read transfers (Cacheable,
> > Bufferable/ Posted). When CCI is enabled in the design, DWC3 core GSBUSCFG0
> > cache bits must be updated to support CCI enabled transfers in USB.
> > 
> > Signed-off-by: Piyush Mehta <piyush.mehta@amd.com>
> > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
> > ----
> > changes for v2:
> > Make GSBUSCFG0 configuration specific to AMD-xilinx platform.
> > Taken reference from existing commit ec5eb43813a4 ("usb: dwc3: core:
> > add support for realtek SoCs custom's global register start address")

Regarding that change from Realtek, it's a special case. I want to avoid
doing platform specific checks in the core.c if possible. Eventually, I
want to move that logic from Realtek to its glue driver.

BR,
Thinh

> > 
> > v1 link:
> > https://urldefense.com/v3/__https://lore.kernel.org/all/20231013053448.11056-1-piyush.mehta@amd.com__;!!A4F2R9G_pg!ffADlNJmRyCb1C2B0z21-8AbJE4YDyiXNxKBKBqmhmBOSSZBokHS_qyetGEqb7Cwawe0Wvbz2aqSZz_bTfvS0cXdwXLVWw$ 
> 
> Please check the comment from the previous thread:
> https://lore.kernel.org/linux-usb/20240223224744.vptvfkqzgqv24ptz@synopsys.com/T/#t
>

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