From: Can Guo <quic_cang@quicinc.com>
Qcom UFS hosts, with HW ver 5, can only support up to HS-G5 Rate-A due to
HW limitations. If the HS-G5 PHY gear is used, update host_params->hs_rate
to Rate-A, so that the subsequent power mode changes shall stick to Rate-A.
Signed-off-by: Can Guo <quic_cang@quicinc.com>
---
drivers/ufs/host/ufs-qcom.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 60b35ca..55ee31d 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -442,9 +442,25 @@ static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba)
static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
{
struct ufs_qcom_host *host = ufshcd_get_variant(hba);
+ struct ufs_host_params *host_params = &host->host_params;
struct phy *phy = host->generic_phy;
+ enum phy_mode mode;
int ret;
+ /*
+ * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations.
+ * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A,
+ * so that the subsequent power mode change shall stick to Rate-A.
+ */
+ if (host->hw_ver.major == 0x5) {
+ if (host->phy_gear == UFS_HS_G5)
+ host_params->hs_rate = PA_HS_MODE_A;
+ else
+ host_params->hs_rate = PA_HS_MODE_B;
+ }
+
+ mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A;
+
/* Reset UFS Host Controller and PHY */
ret = ufs_qcom_host_reset(hba);
if (ret)
@@ -459,7 +475,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
return ret;
}
- phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);
+ phy_set_mode_ext(phy, mode, host->phy_gear);
/* power on phy - start serdes and phy's power and clocks */
ret = phy_power_on(phy);
--
2.7.4
On Mon, Nov 06, 2023 at 08:46:10PM -0800, Can Guo wrote: > From: Can Guo <quic_cang@quicinc.com> > > Qcom UFS hosts, with HW ver 5, can only support up to HS-G5 Rate-A due to > HW limitations. If the HS-G5 PHY gear is used, update host_params->hs_rate > to Rate-A, so that the subsequent power mode changes shall stick to Rate-A. > > Signed-off-by: Can Guo <quic_cang@quicinc.com> > --- > drivers/ufs/host/ufs-qcom.c | 18 +++++++++++++++++- > 1 file changed, 17 insertions(+), 1 deletion(-) > > diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c > index 60b35ca..55ee31d 100644 > --- a/drivers/ufs/host/ufs-qcom.c > +++ b/drivers/ufs/host/ufs-qcom.c > @@ -442,9 +442,25 @@ static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) > static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) > { > struct ufs_qcom_host *host = ufshcd_get_variant(hba); > + struct ufs_host_params *host_params = &host->host_params; > struct phy *phy = host->generic_phy; > + enum phy_mode mode; > int ret; > > + /* > + * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations. Does this limitation apply to future targets as well or just to SM8550? If it's the latter, then we need to use a flag. - Mani > + * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A, > + * so that the subsequent power mode change shall stick to Rate-A. > + */ > + if (host->hw_ver.major == 0x5) { > + if (host->phy_gear == UFS_HS_G5) > + host_params->hs_rate = PA_HS_MODE_A; > + else > + host_params->hs_rate = PA_HS_MODE_B; > + } > + > + mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A; > + > /* Reset UFS Host Controller and PHY */ > ret = ufs_qcom_host_reset(hba); > if (ret) > @@ -459,7 +475,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) > return ret; > } > > - phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear); > + phy_set_mode_ext(phy, mode, host->phy_gear); > > /* power on phy - start serdes and phy's power and clocks */ > ret = phy_power_on(phy); > -- > 2.7.4 > -- மணிவண்ணன் சதாசிவம்
Hi Mani, On 11/8/2023 1:25 PM, Manivannan Sadhasivam wrote: > On Mon, Nov 06, 2023 at 08:46:10PM -0800, Can Guo wrote: >> From: Can Guo <quic_cang@quicinc.com> >> >> Qcom UFS hosts, with HW ver 5, can only support up to HS-G5 Rate-A due to >> HW limitations. If the HS-G5 PHY gear is used, update host_params->hs_rate >> to Rate-A, so that the subsequent power mode changes shall stick to Rate-A. >> >> Signed-off-by: Can Guo <quic_cang@quicinc.com> >> --- >> drivers/ufs/host/ufs-qcom.c | 18 +++++++++++++++++- >> 1 file changed, 17 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c >> index 60b35ca..55ee31d 100644 >> --- a/drivers/ufs/host/ufs-qcom.c >> +++ b/drivers/ufs/host/ufs-qcom.c >> @@ -442,9 +442,25 @@ static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) >> static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) >> { >> struct ufs_qcom_host *host = ufshcd_get_variant(hba); >> + struct ufs_host_params *host_params = &host->host_params; >> struct phy *phy = host->generic_phy; >> + enum phy_mode mode; >> int ret; >> >> + /* >> + * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations. > > Does this limitation apply to future targets as well or just to SM8550? If > it's the latter, then we need to use a flag. > > - ManiUFS host controller HW ver (major) 5 IPs (they may have different minor/step verions) can be used by many QCOM chipsets, so it applies to several available targets and future targets which are going to have HW ver 5 UFS host controller. This limitation goes away since HW ver 6. Thanks, Can Guo.
On Wed, Nov 08, 2023 at 04:42:42PM +0800, Can Guo wrote: > Hi Mani, > > On 11/8/2023 1:25 PM, Manivannan Sadhasivam wrote: > > On Mon, Nov 06, 2023 at 08:46:10PM -0800, Can Guo wrote: > > > From: Can Guo <quic_cang@quicinc.com> > > > > > > Qcom UFS hosts, with HW ver 5, can only support up to HS-G5 Rate-A due to > > > HW limitations. If the HS-G5 PHY gear is used, update host_params->hs_rate > > > to Rate-A, so that the subsequent power mode changes shall stick to Rate-A. > > > > > > Signed-off-by: Can Guo <quic_cang@quicinc.com> > > > --- > > > drivers/ufs/host/ufs-qcom.c | 18 +++++++++++++++++- > > > 1 file changed, 17 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c > > > index 60b35ca..55ee31d 100644 > > > --- a/drivers/ufs/host/ufs-qcom.c > > > +++ b/drivers/ufs/host/ufs-qcom.c > > > @@ -442,9 +442,25 @@ static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) > > > static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) > > > { > > > struct ufs_qcom_host *host = ufshcd_get_variant(hba); > > > + struct ufs_host_params *host_params = &host->host_params; > > > struct phy *phy = host->generic_phy; > > > + enum phy_mode mode; > > > int ret; > > > + /* > > > + * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations. > > > > Does this limitation apply to future targets as well or just to SM8550? If > > it's the latter, then we need to use a flag. > > > > - ManiUFS host controller HW ver (major) 5 IPs (they may have different > minor/step verions) can be used by many QCOM chipsets, so it applies to > several available targets and future targets which are going to have HW ver > 5 UFS host controller. This limitation goes away since HW ver 6. > Okay, thanks for clarifying. - Mani > Thanks, > Can Guo. -- மணிவண்ணன் சதாசிவம்
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