IPQ5018 has tsens V1.0 IP with 4 sensors.
There is no RPM, so tsens has to manually enabled.
Adding the tsens and nvmem node.
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
---
arch/arm64/boot/dts/qcom/ipq5018.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index 9f13d2dcdfd5..277b3cfc7f72 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -93,6 +93,29 @@ soc: soc@0 {
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
+ qfprom_nvmem: qfprom_nvmem@a0000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "qcom,ipq5018-qfprom", "qcom,qfprom";
+ reg = <0xa0000 0x1000>;
+
+ tsens_calib: calib@248 {
+ reg = <0x248 0x10>;
+ };
+ };
+
+ tsens: thermal-sensor@4a9000 {
+ compatible = "qcom,ipq5018-tsens", "qcom,tsens-v1";
+ reg = <0x4a9000 0x1000>, /* TM */
+ <0x4a8000 0x1000>; /* SORT */
+ nvmem-cells = <&tsens_calib>;
+ nvmem-cell-names = "calib";
+ interrupts = <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "uplow";
+ #qcom,sensors = <5>;
+ #thermal-sensor-cells = <1>;
+ };
+
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq5018-tlmm";
reg = <0x01000000 0x300000>;
--
2.34.1
On Mon, 28 Aug 2023 at 22:20, Sricharan Ramabadhran
<quic_srichara@quicinc.com> wrote:
>
> IPQ5018 has tsens V1.0 IP with 4 sensors.
> There is no RPM, so tsens has to manually enabled.
> Adding the tsens and nvmem node.
>
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/ipq5018.dtsi | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> index 9f13d2dcdfd5..277b3cfc7f72 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> @@ -93,6 +93,29 @@ soc: soc@0 {
> #size-cells = <1>;
> ranges = <0 0 0 0xffffffff>;
>
> + qfprom_nvmem: qfprom_nvmem@a0000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "qcom,ipq5018-qfprom", "qcom,qfprom";
> + reg = <0xa0000 0x1000>;
> +
> + tsens_calib: calib@248 {
> + reg = <0x248 0x10>;
> + };
NAK. Please define per-sensor fields here.
> + };
> +
> + tsens: thermal-sensor@4a9000 {
> + compatible = "qcom,ipq5018-tsens", "qcom,tsens-v1";
> + reg = <0x4a9000 0x1000>, /* TM */
> + <0x4a8000 0x1000>; /* SORT */
> + nvmem-cells = <&tsens_calib>;
> + nvmem-cell-names = "calib";
> + interrupts = <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "uplow";
> + #qcom,sensors = <5>;
> + #thermal-sensor-cells = <1>;
> + };
> +
> tlmm: pinctrl@1000000 {
> compatible = "qcom,ipq5018-tlmm";
> reg = <0x01000000 0x300000>;
> --
> 2.34.1
>
--
With best wishes
Dmitry
On 28/08/2023 21:18, Sricharan Ramabadhran wrote:
> IPQ5018 has tsens V1.0 IP with 4 sensors.
> There is no RPM, so tsens has to manually enabled.
> Adding the tsens and nvmem node.
>
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/ipq5018.dtsi | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> index 9f13d2dcdfd5..277b3cfc7f72 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> @@ -93,6 +93,29 @@ soc: soc@0 {
> #size-cells = <1>;
> ranges = <0 0 0 0xffffffff>;
>
> + qfprom_nvmem: qfprom_nvmem@a0000 {
Nope. Come on, where do you see such node naming. Please do not send
code from downstream, but work on upstream sources. Open other most
recent DTS, take a look how it is done and try to do something similar.
> + #address-cells = <1>;
> + #size-cells = <1>;
compatible is always the first property. Then reg.
> + compatible = "qcom,ipq5018-qfprom", "qcom,qfprom";
> + reg = <0xa0000 0x1000>;
> +
> + tsens_calib: calib@248 {
> + reg = <0x248 0x10>;
> + };
> + };
> +
Best regards,
Krzysztof
On 8/29/2023 12:55 AM, Krzysztof Kozlowski wrote:
> On 28/08/2023 21:18, Sricharan Ramabadhran wrote:
>> IPQ5018 has tsens V1.0 IP with 4 sensors.
>> There is no RPM, so tsens has to manually enabled.
>> Adding the tsens and nvmem node.
>>
>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/ipq5018.dtsi | 23 +++++++++++++++++++++++
>> 1 file changed, 23 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>> index 9f13d2dcdfd5..277b3cfc7f72 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>> @@ -93,6 +93,29 @@ soc: soc@0 {
>> #size-cells = <1>;
>> ranges = <0 0 0 0xffffffff>;
>>
>> + qfprom_nvmem: qfprom_nvmem@a0000 {
>
> Nope. Come on, where do you see such node naming. Please do not send
> code from downstream, but work on upstream sources. Open other most
> recent DTS, take a look how it is done and try to do something similar.
>
sure, will fix it up.
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>
> compatible is always the first property. Then reg.
ok, will fix.
Regards,
Sricharan
© 2016 - 2025 Red Hat, Inc.